• Journal of IKEEE
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• v.21 no.4
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• pp.420-423
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• 2017

In this paper, we propose an implementation of a neural network accelerator for reducing the rendering noise. Among the rendering algorithms, we selects a ray tracing to assure a high-definition graphics. Ray tracing rendering uses ray to render. Less use of the ray will result in noise, and if used too much, it will produce a higher quality image, but will take longer. In order to quickly process such lace rendering, an algorithm is used that uses less rays and removes the noise generated. Among such algorithms, there is an algorithm using a neural network, and a neural network accelerator which obtains a filter parameter used in an operation is implemented in order to speed up the operation speed. The time it takes to calculate the parameters used for a pixel is 11.44us.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.105-113
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• 2004

This paper proposes 3D graphics accelerator, especially rendering unit, for portable devices. The existing 3D architecture is not suitable for portable devices because of its huge size. To reduce the size, we use iterative architecture and fixed-point calculation. In this paper, we suggest the format of fixed-point comparing with the result images, and some special technique to control. Finally, it is implemented with FPGA and 0.25um ASIC technology respectively. The ASIC chip can execute 47.88M pixels per second. The size of ASIC chip is 4.9287mm*4.9847mm and the power consumption is 263.7mW with 50MHz operation frequency.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.1
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• pp.10-18
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• 2007

Mobile communication devices such as PDAs, cellular phones, etc., need to perform several kinds of computation-intensive functions including H.264 encoding/decoding and 3D graphics processing. In this paper, new reconfigurable architecture is described, which can perform either motion estimation for H.264 or rendering for 3D graphics. The proposed motion estimation techniques use new efficient SAD computation ordering, DAU, and FDVS algorithms. The new approach can reduce the computation by 70% on the average than that of JM 8.2, without affecting the quality. In 3D rendering, midline traversal algorithm is used for parallel processing to increase throughput. Memories are partitioned into 8 blocks so that 2.4Mbits (47%) of memory is shared and selective power shutdown is possible during motion estimation and 3D graphics rendering. Processing elements are also shared to further reduce the chip area by 7%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.3
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• pp.563-569
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• 2007

As the mobile communication and the semiconductor technology is improved continuously, mobile contents such as the multimedia service and the 2D/3D graphics which require high level graphics are serviced recently. Mobile chips should consume small die area and low power. In this paper, we design a truncated floating-point multiplier that is useful for the 2D/3D vector graphics in mobile devices. The truncated multiplier is based on the radix-4 Booth's encoding algorithm and a truncation algorithm is used to achieve small area and low power. The average percent error of the multiplier is as small as 0.00003% and neglectable for mobile applications. The synthesis result using 0.35um CMOS cell library shows that the number of gates for the truncated multiplier is only 33.8 percent of the conventional radix-4 Booth's multiplier.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.1_2
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• pp.135-143
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• 2004

3D Graphics accelerator is usually composed of two parts, geometry engine and rasterizer. In this paper, VGE(Vector Geometry Engine) which exploits vertex-level parallelism is proposed. In VGE, Common Floating-Point Unit by adding four-FADD, four-FMUL unit and 128-vector register accelerates geometry calculation. In comparison with SH4, Performance result show that the VGE can achieve performance gain over 4.7 times. To evaluate VGE performance, we make simulator to rebuild Simple-Scalar, general purpose processor simulator. In simulator model, we use Viewperf-benchmark.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.53-58
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• 2006

A Vertex Shader is designed to show more 3D graphics expressions, and to increase flexibility of the fixed function T&L (Transform and Lighting) engine. Design of this Shader is based on Vertex Shader 1.1 of DirectX 8.1 and OpenGL ARB. The Vertex Shader consists of four floating point ALUs for vectors operation. The previous 32bits floating point data type is replaced to 24bits floating point data type in order to design the Vertex Shader that consume low-power and occupy small area. A Xilinx Virtex2 300M gate module is used to verify behaviour of the core. The result of Synopsys synthesis shows that the proposed Vertex Shader performs 115MHz speed at the TSMC 0.13um process and it can operate as the rate of 12.5M Polygons/sec. It shows the complexity of 110,000 gates in the same process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.24-33
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• 2006

The effective geometry processing IP architecture for mobile SoC that has real time 3D graphics acceleration performance in mobile information system is proposed. Base on the proposed IP architecture, we design the floating point arithmetic unit needed in geometry process and the floating point geometry processor supporting the 3D graphic international standard OpenGL-ES. The geometry processor is implemented by 160k gate area in a Xilinx-Vertex FPGA and we measure the performance of geometry processor using the actual 3D graphic data at 80MHz frequency environment The experiment result shows 1.5M polygons/sec processing performance. The power consumption is measured to 83.6mW at Hynix 0.25um CMOS@50MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.140-142
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• 2011

In this paper, special purpose arithmetic unit for mobile graphics accelerator is designed. The designed processor supports six operations, such as $1/{\chi}$, $\frac{1}{{\sqrt{x}}$, $log_2x$, $2^x$, $sin(x)$, $cos(x)$. The processor adopts 2nd-order polynomial minimax approximation scheme based on IEEE floating point data format to satisfy accuracy conditions and has 5-stage pipeline structure to meet high operational rates. The SFAU processor consists of 23,000 gates and its estimated operating frequency is about 400 Mhz at operating condition of 65nm CMOS technology. Because the processor can execute all operations with 5-stage pipeline scheme, it has about 400 MOPS(million operations per second) execution rate. Thus, it can be applicable to the 3D mobile graphics processors.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.4
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• pp.727-736
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• 2009

In this paper, the $arccos(cos^{-1})$ arithmetic unit for mobile graphics accelerator is designed. The mobile vector graphics applications need tight area, execution time, power dissipation, and accuracy constraints compared to desktop PC applications. The designed processor adopts 2nd-order polynomial approximation scheme based on IEEE floating point data format to satisfy speed and accuracy conditions and reduces area via hardware sharing structure. The arccosine processor consists of 15,280 gates and its estimated operating frequency is about 125Mhz at operating condition of $0.35{\mu}m$ CMOS technology. Because the processor can execute arccosine function within 7 clock cycles, it has about 17 MOPS(million arccos operations per second) execution rate and can be applicable to mobile OpenVG processor. And because of its flexible architecture, it can be applicable to the various transcendental functions such as exponential, trigonometric and logarithmic functions via replacement of ROM and minor hardware modification.

• Proceedings of the Korean Information Science Society Conference
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• 2001.10c
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• pp.16-18
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• 2001

3차원 영상을 처리하는데 있어 래스터라이제이션은 프레임 버퍼에 저장될 픽셀을 구하는 과정이다. 여러 개의 픽셀로 구성되는 폴리곤을 렌더링하기 위해서 스캔라인 방식 또는 반 평면 함수를 이용한 타일 트래버설 방식 등이 사용되고 있다. 본 논문에서 기반으로 하고 있는 타일 트래버설 방식은 스캔라인 방식에 비해 메모리 효율 및 텍스쳐 캐쉬의 지역성에서 이점을 가지고 있으나 복잡한 탐색 과정 때문에 파이프라인 구조로 구현하기는 어렵다. 본 논문에서 제안하는 구조는 분기 예측 기법을 적용하여 트래버설 과정에서의 분기로 인해 발생되는 파이프라인 지연을 기존의 트래버설 구조에 비해 약 30% 정도 줄임으로써 고성능 3차원 그래픽 가속기에 적합한 스캔 컨버젼 유닛을 제안하였다