• Proceedings of the Korean Operations and Management Science Society Conference
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• 1996.04a
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• pp.100-103
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• 1996

Presented in this study is an algorithmic procedure to obtain polyhedral model from a compound surface. The compound surface in this study denotes a collection of trimmed surfaces without topological relations. The procedure consists of two main modules: CAD data interface, and surface conversion to polyhedral model. The interface module gets geometric information from CAD databases, and makes topological information by scanning the geometric information. We are investigating CATIA system as a data source system. In the surface conversion module, a shell(compound surface with topological information) is approximated to a triangular-faceted polyhedral surface model through node sampling and triangulation steps. The obtained polyhedral model should obey the vertex-to-vertex rule and meet tolerance requirements. Since the polyhedral model has a simple data structure and geometry processing for it is very efficient and robust, the polyhedral model can be used in various applications, such as surface rendering in computer graphics, FEM model for engineering analysis, CAPP for surface machining, data generation for SLA, and NC tool path generation.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2000.04a
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• pp.478-483
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• 2000

In this study to cope with the decreasing product's life-cycle a virtual simulator to realize the simulation environment similar to a real manufacturing line is developed. The developed simulator plays a role in reducing the product conversion time by alternating manufacturing components and work plans on the simulation as manufacturing lines change and actuating a virtual manufacturing lines change and actuating a virtual manufacturing line before a real production. The developed simulator realized a virtual manufacturing line on the simulation using various manipulators and work cells as manufacturing components. Also It can be shown that the simulator can cope with rapid change of a manufacturing line by developing a interface that a separate process is managed for each manufacturing module and a manipulator component and a work cell are changed for a user to become convenient to teach tasks of each work module. using Microsoft Visual C++ 6.0 and OpenGL of Silicon Graphics for libraries to realize 3-dimensional graphic and constructing a database system, a hybrid type of hierachical and relational model to develop a progra that has efficiency and standardization.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.11a
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• pp.1635-1637
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• 2010

Simulation tools help creating a low cost and efficient development of embedded system. SID is an open source simulator software that consists library of components for modelling hardware and software components. A component can be written in C/C++ and Tcl/Tk. Currently, the SID simulation toolkit only provides support for C++ and Tcl/Tk. Tcl/Tk is used to write GUI-based components. However, we have observed that Tcl/Tk components cause slow simulation response because Tcl/Tk is a script language. It is not proper for developing the cutting-edge products with rich graphics. Therefore, in this paper, we suggest Java to a new language for GUI components in SID by developing a bridge module for SID to interworking with Java components.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.1
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• pp.57-62
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• 2006

This treatise proposes a develop system that manufactures 3D clothes model who is used in 3D clothes getting dressed simulation. Need 3D human body model and 3D clothes model to do getting dressed simulation. Create priority work Matrix javelin to design clothes model and design 2D piece from designer Connect designed piece plain using backstitch line and create numerical value data because using designed piece and backstitch data finally and make 3D clothes model. Consist of piece design module, to read clothes data and save module, getting dressed simulation module in system that propose in this treatise.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.1-6
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• 2002

In this paper, an Analog Flat Panel interface(AFPI) which supports for UXGa(Ultar extended Graphics Array)-Compatible TFT LCD Driver is designed. The Proposed AFPI is composed of 8-b ADC, Automatic Gain Control(AGC), Low-Jitter PLL. In order to obtain a high speed and low power consumption, an efficient architecture of 8-bit ADC is proposed, whose FR(Folding Rate) is 8, NFB(Number of Folding Block) is 2, and IR (Interpolating Rate) is 16. We can get high SNDR by adopting distributed track and hold circuits. Also a programmable AGC which is possible to control gain and clamp, and a low-jitter PLL are proposed. The chip has been fabricated with 0.25${\mu}{\textrm}{m}$ 1-poly S-metal n-well CMOS technology. The effective chip area is 3.6mm $\times$ 3.2mm and it dissipates about 602㎽ at 2.5V power supply. The INL and DNL are within $\pm$ 1LSB. The measured SNDR is about 43㏈, when the input frequency is 10MHz at 200MHz clock frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.121-124
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• 2007

This paper describes the development of a brickwork game with three-dimensional computer graphics as one of web-based game contents. Client user using web can access and run lava applet program with the independence of hardware system. It consists of graphic user interface module, initial space generation module, event handler module, player control module, and thread control module. It uses 3-D array data structure for the 3-D graphic objects that are located in three-dimensional space for high-speed object searching and sorting. It enhances to compare with predetermined construction in three-dimensional space. We can use the developed racing game to inform game users of information for an advertisement like tourism information, and can apply the proposed 3-D drawing technology to 3-D game graphic engine core.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.135-141
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• 2013

In this paper, we installed three high brightness red, green, and blue LED in one socket and made one pixel unit. And we also developed the full-color display board module and control unit which can express various images such as text, graphics, video image with the combination of pixel units and a number of modules. LED display driver module have a driver circuit within the combination of the RGB pixel dot on unit area. These modules of the existing form can be high priced because of implementation a fixed resolution in specific space and installation space. To overcome these shortcomings, we developed a LED driver and LED pixel modules free in array at random pitch intervals. Display board module of this paper enabled to display smoothly video image which have many data processing quantity through dragging data speed up 36 frames per second. Also there are an effect which is provided more clear image because of improving the flickering of the existing display board.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.321-324
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• 2010

There have been lots of researches on a multi-core processor. The enhancement has been performed through parallelization method. Multi-core architecture in the mobile environment has emerged. But, there is a limit to a mobile CPU's performance. GP-GPU(General-Purpose computing on Graphics Processing Units) can improve performance without adding other dedicated hardware. This paper presents the implementation of Inverse Quantization, Inverse DCT and Color Space Conversion module in H.264/AVC decoder using Multi-Core GP-GPU for a mobile environments. The proposed architecture improves approximately 50% of performance when it use all the features.

• Korean Journal of Remote Sensing
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• v.10 no.2
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• pp.121-132
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• 1994

A GIS based tactical terrain analysis system named ATTAS(Army Tactical Terrain Analysis Software) has been designed and implemented to support the field commanders for enhancing the capabiliy of their unit and efficiency of weapon system. This system is designed to provide computer graphics environment in which the analyst can interactively operate the entire analyzing process such as selecting the area of interest, performing analysis functions, simulating required battlefield operation and display the results. This system can be divided into three major sections; the terrain analysis modules, utilites, and graphic editor. The terrain analysis module inclused surface analysis, line of sight analysis, enemy disposition, 3D display, radar coverage, logistic route analysis, shortest path analysis, atmospheric phenomena prediction, automated IPB (Inteligence preparation of Battlefield), and other applied analysis. A combination of 2D and 3D computer graphics techniques using the X-window system with OSF/Motif in UNIX workstation was adopted as the user interface. The integration technique of remotely sensed images and GIS data such as precision registration, overlay, and on-line editing was developed and implemented. An efficient image and GIS data management technique was also developed and implemented using Oracle Database Management System.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.53-58
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• 2006

A Vertex Shader is designed to show more 3D graphics expressions, and to increase flexibility of the fixed function T&L (Transform and Lighting) engine. Design of this Shader is based on Vertex Shader 1.1 of DirectX 8.1 and OpenGL ARB. The Vertex Shader consists of four floating point ALUs for vectors operation. The previous 32bits floating point data type is replaced to 24bits floating point data type in order to design the Vertex Shader that consume low-power and occupy small area. A Xilinx Virtex2 300M gate module is used to verify behaviour of the core. The result of Synopsys synthesis shows that the proposed Vertex Shader performs 115MHz speed at the TSMC 0.13um process and it can operate as the rate of 12.5M Polygons/sec. It shows the complexity of 110,000 gates in the same process.