• Title/Summary/Keyword: Graphic processor

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Development of a Pre/Post Processor Program for the Analysis of the Passenger Flow based on Discrete Element Method(DEM) (DEM에 기초한 여객유동 해석을 위한 전/후처리 프로그램 개발)

  • Kim, Chi-Gyeom;Won, Chan-Shik;Hur, Nahm-Keon;Nam, Seong-Won
    • Proceedings of the SAREK Conference
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    • 2008.11a
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    • pp.475-480
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    • 2008
  • A pre/post processor program based GUI(Graphic User Interface) by using the MFC and OpenGL library in the Windows OS have been developed for the analysis of the passenger flow. Using this program, users are able to generate and modify the meshes of multi-storied subway station, set all the parameters for the solver, and obtain the results of the simulation such as transient passenger motions and passenger streak lines in 3-dimensional graphic view.

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A Design of LED Video Processor Board using Embedded System (임베디드 시스템을 이용한 LED 비디오 프로세서 설계)

  • Lee, Jong-Ha;Ko, Duck-Young
    • 전자공학회논문지 IE
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    • v.47 no.3
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    • pp.1-6
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    • 2010
  • In this paper, it is designed a processor using embedded system so that moving picture can be expressed on LED electric sign board which has been expressed a simple message only like as a character or graphic. It has been fabricated a moving picture LED electric sign board which is composed to a video processor and LED display panel, in order to be able to express a digital moving picture of 24 bits that is transmitted from embedded system. It includes gamma adjustment, brightness, color contrast control, a schedule function, expression image conversion by the Internet and memory device. Also, an application program based Windows CE is designed so that a character, graphic, and moving picture can be expressed on a small LED electric sign board.

DEVELOPMENT OF THE PRE-PROCESSOR FOR CFD (CFD용 전처리장치 개발)

  • Kim, S.R.
    • Journal of computational fluids engineering
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    • v.18 no.2
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    • pp.72-77
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    • 2013
  • The Pre-processor program for CFD is being developed using wxWidgets and OpenGL libraries. This program can be run on both Windows and Linux operating systems. Undergraduate students and beginners can learn and use this very easily by menu and templates. Until now, structured mesh can be created in Cartesian or Cylindrical coordinates. This program will be used easily to make various type of meshes using templates.

A design of transcendental function arithmetic unit for lighting operation of mobile 3D graphic processor (모바일 3차원 그래픽 프로세서의 조명처리 연산을 위한 초월함수 연산기 구현)

  • Lee, Sang-Hun;Lee, Chan-Ho
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.715-718
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    • 2005
  • Mobile devices is getting to include more functions according to the demand of digital convergence. Applications based on 3D graphic calculation such as 3D games and navigation are one of the functions. 3D graphic calculation requires heavy calculation. Therefore, we need dedicated 3D graphic hardware unit with high performance. 3D graphic calculation needs a lot of complicated floating-point arithmetic operation. However, most of current mobile 3D graphics processors do not have efficient architecture for mobile devices because they are based on those for conventional computer systems. In this paper, we propose arithmetic units for special functions of lighting operation of 3D graphics. Transcendental arithmetic units are designed using approximation of logarithm function. Special function units for lighting operation such as reciprocal, square root, reciprocal of square root, and power can be obtained. The proposed arithmetic unit has lower error rate and smaller silicon area than conventional arithmetic architecture.

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Assistant Professor, Department of Computer Engineering Pukyong Universisty (한국형 방송 프로그램 시스템 디코더 ASSP의 개발)

  • Jo, Gyeong-Yeon
    • The Transactions of the Korea Information Processing Society
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    • v.3 no.5
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    • pp.1229-1239
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    • 1996
  • The increase of additional information broadcasting of TV demands a graphic overlay processor. This paper is about the design, implementation and testing of a graphic overlay processor called by KBPS decoder ASSP (Applicatio n Specific Standard Product) which is compliance with Korea Broadcast Programming System. KBPS decoder ASSP consists of embedded 8 bit microprocessor Z80, graphic overlay controller, KBPS schedule decoder, memory controller, priority interrupt controller, MIDI controller, infrared raccoon receiver, async scrial communication controller, timer, bus controller, universal parallel input-output port and serial-parallel interface. The 0.8 micron CMOS Sea of Gate is used to implement the ASSP in amount of about 31,500 gates, and it is running at 14.318MHz.

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Accelerating the Sweep3D for a Graphic Processor Unit

  • Gong, Chunye;Liu, Jie;Chen, Haitao;Xie, Jing;Gong, Zhenghu
    • Journal of Information Processing Systems
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    • v.7 no.1
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    • pp.63-74
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    • 2011
  • As a powerful and flexible processor, the Graphic Processing Unit (GPU) can offer a great faculty in solving many high-performance computing applications. Sweep3D, which simulates a single group time-independent discrete ordinates (Sn) neutron transport deterministically on 3D Cartesian geometry space, represents the key part of a real ASCI application. The wavefront process for parallel computation in Sweep3D limits the concurrent threads on the GPU. In this paper, we present multi-dimensional optimization methods for Sweep3D, which can be efficiently implemented on the finegrained parallel architecture of the GPU. Our results show that the overall performance of Sweep3D on the CPU-GPU hybrid platform can be improved up to 4.38 times as compared to the CPU-based implementation.

A Design of Floating-Point Geometry Processor for Embedded 3D Graphics Acceleration (내장형 3D 그래픽 가속을 위한 부동소수점 Geometry 프로세서 설계)

  • Nam Ki hun;Ha Jin Seok;Kwak Jae Chang;Lee Kwang Youb
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.2 s.344
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    • pp.24-33
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    • 2006
  • The effective geometry processing IP architecture for mobile SoC that has real time 3D graphics acceleration performance in mobile information system is proposed. Base on the proposed IP architecture, we design the floating point arithmetic unit needed in geometry process and the floating point geometry processor supporting the 3D graphic international standard OpenGL-ES. The geometry processor is implemented by 160k gate area in a Xilinx-Vertex FPGA and we measure the performance of geometry processor using the actual 3D graphic data at 80MHz frequency environment The experiment result shows 1.5M polygons/sec processing performance. The power consumption is measured to 83.6mW at Hynix 0.25um CMOS@50MHz.

Design of Special Function Unit for Vectorized SIMD Programmable Unified Shader (벡터화된 SIMD 프로그램어블 통합 셰이더를 위한 특수 함수 유닛 설계)

  • Jung, Jin-Ha;Kim, Kyeong-Seob;Yun, Jeong-Hee;Seo, Jang-Won;Choi, Sang-Bang
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.5
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    • pp.56-70
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    • 2010
  • Rendering technique generating 2 dimensional image to give reality and high performance graphical processor for efficient processing of massive data are necessary to support realistic 3 dimensional graphical image. Recently, graphical hardwares have evolved rapidly. This enables high quality rendering effect that we were unable to process in realtime. Improving shading technique enabled us to render realistic images but still much time is required for this process. Multiple operational units are being integrated in a graphical processor for effective floating point operation using massive data to process almost real looking images. In this paper, we have designed and implemented a special functional unit to support high quality 3 dimensional computer graphic image on programmable integrated shader processor. We have done evaluation through functional level simulation of designed special functional unit. Hardware resource usage rate and execution speed are measured implementing directly on FPGA Virtex-4(xc4vlx200).

Design of an On-Chip Multiprocessor (단일 칩 다중프로세서의 설계)

  • 이상원;김영우
    • Proceedings of the IEEK Conference
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    • 1998.10a
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    • pp.751-754
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    • 1998
  • This research aims at developing a single chip multiprocessor for high-performance computer system. Our design approach is to design a relatively small and simple processor unit and to integrate multiple copies of the unit in an efficient way. The proposed multiprocessor is composed of four CPUs and one graphic coprocessor. The four CPUs share the graphic coprocessor and each CPU implements the 64-bit SPARC-V9 instruction set architecture. This paper gives an overview of the proposed microarchitecture and discusses the considerations made in the course of the design.

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A study on the Development of Structural Analysis Program using Visual Basic (Visual Basic을 이용한 구조해석 프로그램 개발에 관한 연구)

  • 이상갑;장승조
    • Proceedings of the Computational Structural Engineering Institute Conference
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    • 1995.10a
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    • pp.215-222
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    • 1995
  • The objective of this paper is to develop a finite element structural analysis program using VB(Visual Basic) which has been recently getting popular as development tools of application program for Windows. VB provides several functions to develop an application program easily by supporting event-driven programming method and graphic object as control data type. This system is an integrated processor including preprocessor, solver and postprocessor. Automatic mesh generation is available at preprocess stage, and graphic presentation of deformation and stress is also represented at postprocess one.

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