• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.9A
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• pp.1434-1441
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• 1999

This paper presents an equivalent circuit of the hairpin line filter for accurate analysis and design. Its validity was verified by computer simulations and filter design experiments. Though the various design equations for a hairpin line filter have been proposed, there has not been a practically simplified equivalent circuit because it is hard to effectively represent interconnection effects between non-adjacent elements. In this paper, all the open ports of the hairpin line filter circuit are changed to the short ports using circuit duality, and the resulting circuits are transformed to graph model. The further simplified circuit model is obtained from boundary conditions, and then the final equivalent circuit of the hairpin line filter is derived in a dual structure of the filter.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.9 no.3
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• pp.85-93
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• 2010

This paper proposes a new dynamic hardware allocation and binding algorithm of a simultaneous allocation and binding for SOC design automation. The proposed algorithm works on scheduled input graph and simultaneously allocates binds functional units, interconnections and registers by considering interdependency between operations and storage elements in each control step, in order to share registers and interconnections connected to functional units, as much as possible. This paper shows the effectiveness of the proposed algorithm by comparing experiments to determine number of function unit in advance or by comparing separated executing allocation and binding of existing system.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.1
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• pp.40-51
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• 2009

A paired many-to-many k-disjoint path cover (paired k-DPC) of a graph G is a set of k disjoint paths joining k distinct source-sink pairs in which each vertex of G is covered by a path. In this paper, we investigate disjoint path covers in recursive circulants G($cd^m$,d) with $d{\geq}3$ and tori, and show that provided the number of faulty elements (vertices and/or edges) is f or less, every nonbipartite recursive circulant and torus of degree $\delta$ has a paired k-DPC for any f and $k{\geq}1$ with $f+2k{\leq}{\delta}-1$.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.8
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• pp.426-431
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• 2005

A many-to-many k-disjoint path cover (k-DPC) of a graph G is a set of k disjoint paths joining k distinct source-sink pairs in which each vertex of G is covered by a path. In this paper, we investigate many-to-many 2-DPC in a double loop network G(mn;1,m), and show that every nonbipartite G(mn;1,m), $m{\geq}3$, has 2-DPC joining any two source-sink pairs of vertices and that every bipartite G(mn;1,m) has 2-DPC joining any two source-sink pairs of black-white vertices and joining any Pairs of black-black and white-white vertices. G(mn;l,m) is bipartite if and only if n is odd and n is even.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.31 no.4
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• pp.731-751
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• 2021

The Internet of Things is a huge group of devices communicating each other and the interconnection of objects in the network is a basic requirement. Choosing a reliable device is critical because malicious devices can compromise networks and services. However, it is difficult to create a trust management model due to the mobility and resource constraints of IoT devices. For the centralized approach, there are issues of single point of failure and resource expansion and for the distributed approach, it allows to expand network without additional equipment by interconnecting each other, but it has limitations in data exchange and storage with limited resources and is difficult to ensure consistency. Recently, trust management models using fog nodes and blockchain have been proposed. However, blockchain has problems of low throughput and delay. Therefore, in this paper, a trust management model for selecting reliable devices in a fog-based IoT environment is proposed by applying IOTA, a blockchain technology for the Internet of Things. In this model, Directed Acyclic Graph-based ledger structure manages trust data without falsification and improves the low throughput and scalability problems of blockchain.

• Fire Science and Engineering
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• v.28 no.3
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• pp.72-79
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• 2014

The purpose of this study is to draw the improvement plan through the analysis of problems of main stretchers that are being used by the 119 EMS. In order to find out the problems, we used the literature review and analysis, survey questionnaire and we also made full use of KJ method (Kawakita Jiro method, affinity diagram), graph method, and priority matrix method to produce the improvement indicators. The problems of main stretchers are summarized as follows. they are being recognized as part of the emergency vehicle, they have the imperfection of performance verification criteria, and they cause the injuries of paramedics and patients accidents in operation. The indicators such as the ease of operation, the high performance, the multi-function, the driving performance, the durability and the lightweight, was produced to improve the problems. The results of the interconnection analysis and the applying priority matrix method on the indicators are the ease of operation ${\rightarrow}$ the multi-function ${\rightarrow}$ the driving performance ${\rightarrow}$ the high performance ${\rightarrow}$ the durability and the lightweight in order of importance.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.8
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• pp.1009-1023
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• 1999

이 논문은 재귀원형군 G(2^m , 2^k ) 그래프 이론적 관점에서 고찰하고 정점이 서로소인 경로에 관한 위상 특성을 제시한다. 재귀원형군은 1 에서 제안된 다중 컴퓨터의 연결망 구조이다. 재귀원형군 {{{{G(2^m , 2^k )의 서로 다른 두 노드 v와 w를 잇는 연결도 kappa(G)개의 서로소인 경로의 길이가 두 노드 사이의 거리d(v,w)나 혹은 G(2^m , 2^k )의 지름 \dia(G)에 비해서 얼마나 늘어나는지를 고려한다. 서로소인 경로를 재귀적으로 설계하는데, 그 길이는 k ge2일 때 d(v,w)+2^k-1과 \dia(G)+2^k-1의 최솟값 이하이고, k=1일 때 d(v,w)+3과 \dia(G)\+2의 최솟값 이하이다. 이 연구는 (2^m , 2^k )의 고장 감내 라우팅, 고장 지름이나 persistence의 분석에 이용할 수 있다.Abstract In this paper, we investigate recursive circulant G(2^m , 2^k ) from the graph theory point of view and present topological properties concerned with node-disjoint paths. Recursive circulant is an interconnection structure for multicomputer networks proposed in 1 . We consider the length increments of {{{{kappa(G)disjoint paths joining arbitrary two nodes v and win G(2^m , 2^k )compared with distance d(v,w)between the two nodes and diameter {{{{\dia(G)of G(2^m , 2^k ), where kappa(G)is the connectivity of G(2^m , 2^k ). We recursively construct disjoint paths of length less than or equal to the minimum of {{{{d(v,w)+2^k-1and \dia(G)+2^k-1for kge2 and the minimum of d(v,w)+3 and \dia(G)+2for k=1. This work can be applied to fault-tolerant routing and analysis of fault diameter and persistence of G(2^m , 2^k )

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.17-28
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• 1999

In this paper, an ASIC emulation system called ACE (ASIC Emulator) is proposed. It can produce the prototype of target ASIC in a short time and verify the function of ASIC circuit immediately The ACE is consist of emulation software in which there are EDIF reader, library translator, technology mapper, circuit partitioner and LDF generator and emulation hardware including emulation board and logic analyzer. Technology mapping is consist of three steps such as circuit partitioning and extraction of logic function, minimization of logic function and grouping of logic function. During those procedures, the number of basic logic blocks and maximum levels are minimized by making the output to be assigned in a same block sharing product-terms and input variables as much as possible. Circuit partitioner obtain chip-level netlists satisfying some constraints on routing structure of emulation board as well as the architecture of FPGA chip. A new partitioning algorithm whose objective function is the minimization of the number of interconnections among FPGA chips and among group of FPGA chips is proposed. The routing structure of emulation board take the advantage of complete graph and partial crossbar structure in order to minimize the interconnection delay between FPGA chips regardless of circuit size. logic analyzer display the waveform of probing signal on PC monitor that is designated by user. In order to evaluate the performance of the proposed emulation system, video Quad-splitter, one of the commercial ASIC, is implemented on the emulation board. Experimental results show that it is operated in the real time of 14.3MHz and functioned perfectly.