• Journal of Korean Vacuum Science & Technology
• /
• v.3 no.1
• /
• pp.74-78
• /
• 1999

For a high efficient field emission display (FED), the specific vacuum conditions below 10-7 Torr should be required. However, because the FED has the geometrical restriction due to its micro size, the thin film getters can be proposed for chemical pumping as a way to reduce impurity gases in the panel. The thin film getters, developed by employing the coating of new materials such as NI or Pt on getter surface, can be used without any activation process and show the enhanced sorption characteristics. Especially, using the Zr (1${\mu}{\textrm}{m}$) thin film getters with the Pt surface layer, the significant gettering for various active gases could be achieved from 9$\times$10-5 Torr to 1$\times$10-6 Torr or below. this good sorption properties is mainly contributed to the surface coating layer which shows the catalytic effect for gas dissociation and protects the getter materials against oxidation.

• Electrical & Electronic Materials
• /
• v.10 no.10
• /
• pp.1034-1040
• /
• 1997

A solar cell conversion effiency was degraded by grain boundary effect in polycrystalline silicon. Grain boundaries acted as potential barriers as well as recombination centers for the photo-generated carriers. To reduce these effects of the grain boundaries we investigated various influencing factors such as emitter thickness thermal treatment preferential chemical etching of grain boundaries grid design contact metal and top metallization along boundaries. Pretreatment in $N_2$atmosphere and gettering by POCl$_3$and Al were performed to obtain multicrystalline silicon of the reduced defect density. Structural electrical and optical properties of slar cells were characterized before and after each fabrication process. Improved conversion efficiencies of solar cell were obtained by a combination of pretreatment above 90$0^{\circ}C$ emitter layer of 0.43${\mu}{\textrm}{m}$ Al diffusion in to grain boundaries on rear side fine grid finger top Yb metal and buried contact metallization along grain boundaries.

• Proceedings of the KIEE Conference
• /
• 1997.07d
• /
• pp.1430-1432
• /
• 1997

A solar cell conversion effiency was degraded by grain boundary effect in polycrystalline silicon. To reduce these effects of the grain boundaries, we investigated various influencing factors such as preferential chemical etching of grain boundaries, grid design, transparent conductive thin film, and top metallization along grain boundaries. Pretreatment in $N_2$ atmosphere and gettering by $POCl_3$ and Al were performed to obtain polycrystalline silicon of the reduced defect density. Structural, electrical, and optical properties of solar cells were characterized. Improved conversion efficiencies of solar cell were obtained by a combination of Al diffusion into grain boundaries on rear side, fine grid finger, top Yb metal grid on Cr thin film of $200{\AA}$ and buried contact metallization along grain boundaries.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.11 no.9
• /
• pp.705-710
• /
• 1998

Intrinsic gettering is usually to improve wafer quality, which is an important factor for reliable ULSI devices. In order to generate oxygen precipitation in lightly and heavily boron doped silicon wafers with or without high $^75 As^+$ ion implantation, the 2-step annealing method was adopted. After annealing, the were cleaved and etched with th Wright etchant. The morphology of cross section on samples was inspected by FESEM(field emission scanning electron microscopy). The morphology of unimplanted samples was rater rough than that of the implanted. Oxygen precipitation density observed by an optical microscope in lightly boron doped samples was about 3$\times10^6/cm^3$. However, in heavily boron doped samples, the density of oxygen precipitation was largest at $600^{\circ}C$ in 1st annealing, and decreased abruptly until $800^{\circ}C$, But it increased slightly at $1000^{\circ}C$ and was independent with the implantation.

• Journal of the Semiconductor & Display Technology
• /
• v.1 no.1
• /
• pp.15-19
• /
• 2002

A new vacuum packaging process in wafer level is developed for the surface micromachining devices using glass silicon anodic bonding technology. The inside pressure of the packaged device was measured indirectly by the quality factor of the mechanical resonator. The measured Q factor was about 5$\times10^4$ and the estimated inner pressure was about 1 mTorr. And it is also possible to change the inside pressure of the packaged devices from 2 Torr to 1 mTorr by varying the amount of the Ti gettering material. The long-term stability test is still on the way, but in initial characterization, the yield is about 80% and the vacuum degradation with time was not observed.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.25 no.12
• /
• pp.1656-1662
• /
• 1988

Auger depth profiles of various In Ga As P/In P heterojunctions grown by liquid phase epitaxial techniques under different growth conditions such as diffusion temperature, diffusion time and dopants, have been obtained. The surface contaminations of In Ga As have been investigated. We found that the samples with Zn diffusion exhibit significant interface grading phenomena including In depletion, Ga richness and P richness at the In Ga As P/In P interface, and In outdiffusion at the surface. The main surface contamination was found to be due to carbon and oxygen species. It can be suggested that Zn gettering takes a major role in such phenomena as interface grading, in depletion, and Ga and P richness at the interface.

• Journal of the Korean Ceramic Society
• /
• v.36 no.8
• /
• pp.863-870
• /
• 1999

SOI(silicon on insulafor) was fabricated through the direct bonding using (100) Si wafer and 4$^{\circ}$off (100) Si wafer to investigate the stacking faults in silicon at the Si/SiO2 oxidized and bonded interface. The treatment time of wafer surface using MSC-1 solution was varied in order to observe the effect of cleaning on bonding characteristics. As the MSC-1 treating time increased surface hydrophilicity was saturated and surface microroughness increased. A comparison of surface hydrophilicity and microroughness with MSC-1 treating time indicates that optimum surface modified condition for time was immersed in MSC-1 for 2 min. The SOI structure directly bonded using (100) Si wafer and 4$^{\circ}$off (100) Si wafer at the room temperature were annealed at 110$0^{\circ}C$ for 30 min. Then the stacking faults at the bonding and oxidation interface were examined after the debonding. The results show that there were anomalies in the gettering of the stacking faults at the bonded region.

• Journal of the Microelectronics and Packaging Society
• /
• v.19 no.4
• /
• pp.71-78
• /
• 2012

This paper describes trends in conventional scaling compared with advanced technologies such as 3D integration (3DI) and bumpless through-silicon via (TSV) processes, as well as the characteristics of CMOS (Complementary Metal Oxide Semiconductor) Logic device after thinning the wafers to less than $10{\mu}m$. Each module process including thinning, stacking, and TSV, is optimized for 3D Wafer-on-Wafer (WOW) application. Optimization results are discussed with valuable data in detail. Since vertical wiring of bumpless TSV can be connected directly to the upper and lower substrates by self-alignment, bumps are not necessary when TSV interconnects are used.

• Proceedings of the KIEE Conference
• /
• 1998.07d
• /
• pp.1361-1363
• /
• 1998

Poly-Si grain boundaries act as potential barriers as well as recombination centers for the photo-generated carriers in solar cells. Thereby, grain boundaries of poly-Si are considered as a major source of the poly-Si cell efficiency was reduced This paper investigated grain boundary effect of poly-Si wafer prior to the solar cell fabrication. By comparing I-V characteristics inner grain, on and across the grain boundary, we were able to detect grain potentials. To reduce grain boundary effect we carried out pretreatment, $POCl_3$ gettering, and examined carrier lifetime. This paper focuses on resistivity variation effect due to grain boundary of poly-Si. The resistivity of the inner grain was $2.2{\Omega}-cm$, on the grain boundary$2.3{\Omega}-cm$, across the grain boundary $2.6{\Omega}-cm$. A measured resistivity varied depending on how many grains were included inside the four point probes. The resistivity increased as the number of grain boundaries increased. Our result can contribute to achieve high conversion efficiency of poly-Si solar cell by overcoming the grain boundary influence.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2000.05b
• /
• pp.171-174
• /
• 2000

We have investigated the CMP slurry properties of silicate oxide thin films surface on CMP cleaning process. The metallic contaminations by CMP slurry were evaluated in four different oxide films, such as plasma enhanced tetra-ethyl-ortho-silicate glass(PE-TEOS), $O_3$ boro-phospho silicate giass( $O_3$-BPSG), PE-BPSG, and phospho-silicate glass(PSG). All films were polished with KOH-based slurry prior to entering the post-CMP cleaner. The Total X-Ray Fluorescence(TXRF) measurements showed that all oxide surfaces are heavily contaminated by potassium and calcium during polishing, which is due to a CMP slurry. The polished $O_3$-BPSG films presented higher potassium and calcium contaminations compared to PE-TEOS because of a mobile ions gettering ability of phosphorus. For PSG oxides, the slurry induced mobile ion contamination increased with an increase of phosphorus contents.