• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.21-22
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• 2005

Partially-depleted Silicon on insulator metal-oxide-semiconductor field- effect transistors (PD-SOI MOSFETs) with Silicon-germanium (SiGe) layer is investigated. This structure uses SiGe layer to reduce the kink effect in the floating body region near the bottom channel/buried oxide interface. Among many design parameters influencing the performance of the device, Ge composition is presented most predominant effects, simulation results show that kink effect is reduced with increase the Ge composition. Because the bandgap of SiGe layer is reduced at higher Ge composition, the hole current between body and SiGe layer is enhanced.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.21 no.4
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• pp.153-157
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• 2011

We have investigated the effect of inductively coupled plasma (ICP) treatment on the early growth stage of heteroepitaxial Ge layers grown on Si(100) substrates using low pressure chemical vapor deposition (LPCVD), The Si(100) substrates were treated by ICP process with various source and bias powers, followed by the Ge deposition, The ICP treatment led to the enhancement in the coalescence of Ge islands, The growth rate of Ge on Si(100) with ICP surface treatment is about 5 times higher than that without ICP surface treatment. A missing dimer caused by the ICP surface treatment can act as a nucleation site for Ge adatoms, which could be responsible for the improvement in growth behavior of Ge on Si(100) substrates.

• Journal of the Korean Vacuum Society
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• v.16 no.2
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• pp.145-152
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• 2007

The evolution dynamics of nanoscale Ge islands on both Si (001) and (113) surfaces is explored using ultraviolet photoelectron emission microscopy (UV-PEEM). Real-time monitoring of the in-situ growth of the Ge island structures can allow us to study the variation of the size, the shape and the density of the nanostructures. For Ge depositions greater than ${\sim}4$ monolayer (ML) with a growth rate of ${\sim}0.4\;ML/min$ at temperatures of $450-550^{\circ}C$, we observed island nucleation on both surfaces indicating the transition from strained layer to island structure. During continuous deposition the circular islands grew larger via ripening processes. AFM measurements showed that the islands grown on Si (001) were dome-shaped while the islands on Si (113) were multiple-side faceted with flat tops of (113)-orientation. In contrast, for Ge deposition with a lower growth rate of ${\sim}0.15\;ML/min$ on Si(113), we observed the shape transition from circular into elongated island structures. The elongated islands grew longer along the [$33\bar{2}$] during continuous Ge deposition. The shape evolution of the islands is discussed in terms of strain relaxation and kinetic effects.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.113-114
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• 2007

Hole mobility characteristics of single surface channel and dual channel Si/SiGe structure are compared, where the former one consists of a relaxed SiGe buffer layer and a tensile strained Si layer on top, and for dual channel structure a compressively strained SiGe layer is inserted between them. Due to the difference of hole mobility enhancement factors of layers between them, hole mobility characteristics with respect to the Si cap thickness shows the opposite tend. Hole mobility increases with thicker Si cap for single channel structure, whereas it decreases with thicker Si cap for dual channel structure.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.264-275
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• 2008

Electron mobility has been investigated theoretically in undoped double-gate (DG) MOSFETs of different channel architectures: a relaxed-Si DG SOI, a strained-Si (sSi) DG SSOI (strained-Si-on-insulator, containing no SiGe layer), and a strained-Si DG SGOI (strained-Si-on-SiGe-on-insulator, containing a SiGe layer) at 300K. Electron mobility in the DG SSOI device exhibits high enhancement relative to the DG SOI. In the DG SGOI devices the mobility is strongly suppressed by the confinement of electrons in much narrower strained-Si layers, as well as by the alloy scattering within the SiGe layer. As a consequence, in the DG SGOI devices with thinnest strained-Si layers the electron mobility may drop below the level of the relaxed DG SOI and the mobility enhancement expected from the strained-Si devices may be lost.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.6
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• pp.491-495
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• 2007

This paper has demonstrated the electrical properties of SiGe pMOSFETs fabricated on both bulk-Si and PD SOI substrates. Two principal merits, the mobility increase in strained-SiGe channel and the parasitic capacitance reduction of SOI isolation, resulted in improvements in device performance. It was observed that the SiGe PD SOI could alleviate the floating body effect, and consequently DIBL was as low as 10 mV/V. The cut-off frequency of device fabricated on PD SOI substrate was roughly doubled in comparison with SiGe bulk: from 6.7 GHz to 11.3 GHz. These experimental result suggests that the SiGe PD SOI pMOSFET is a promising option to drive CMOS to enhance performance with its increased operation frequency for high speed and low noise applications.

• Electrical & Electronic Materials
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• v.8 no.1
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• pp.71-76
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• 1995

The thermal oxidation of Ge$_{0.2}$Si$_{0.8}$ in wet ambient has been investigated by Rutherford Backscattering Spectrometry(RBS). A uniform Ge$_{0.2}$Si$_{0.8}$O$_{2}$ oxide is formed at temperatures below 650.deg. C for polycrystalline and below 700.deg. C for single crystalline substrates. At higher temperatures Ge becomes depleted from the oxide and finally SiO$_{2}$ oxide is formed with Ge piled-ub behind it. The transition between the different oxide types depends also on the crystallinity of Ge$_{0.2}$Si$_{0.8}$. When a uniform Ge$_{0.2}$Si$_{0}$8/O$_{2}$ oxide grows, its thickness is proportional to the square root of the oxidation time, which suggests that the rate noting process is the diffusive transport of oxidant across the oxide. It is believed the oxidation is controlled by the competition between the diffusion of Ge or Si in Ge$_{0.2}$Si$_{0.8}$ and the movement of oxidation front.t.oxidation front.t.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.136-147
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• 2005

A theoretical design evaluation based on a hydrodynamic transport simulation of strained Si-SiGe on insulator (SSOI) type nMOSFETs is reported. Although, the net performance improvement is quite limited by the short channel effects, simulation results clearly show that the strained Si-SiGe type nMOSFETs are well-suited for gate lengths down to 20 nm. Simulation results show that the improvement in the transconductance with decreasing gate length is limited by the long-range Coulomb scattering. An influence of lateral and vertical diffusion of shallow dopants in the source/drain extension regions on the device performance (i.e., threshold voltage shift, subthreshold slope, current drivability and transconductance) is quantitatively assessed. An optimum layer thickness ($t_{si}$ of 5 and $t_{sg}$ of 10 nm) with shallow Junction depth (5-10 nm) and controlled lateral diffusion with steep doping gradient is needed to realize the sub-50 nm gate strained Si-SiGe type nMOSFETs.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.743-746
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• 2003

We have successfully used hydrophobic direct-wafer bonding, along with H-induced layer splitting of Ge, to transfer 700nm think, single-crystal Ge films to Si substrates. Optical and electrical properties have been also observed on these samples. Triple-junction solar cell structures gown on these Ge/Si heterostructure templates show comparable photoluminescence intensity and minority carrier lifetime to a control structure grown on bulk Ge. When heavily doped p$^{+}$Ge/p$^{+}$Si wafer bonded heterostructures were bonded, ohmic interfacial properties with less than 0.3Ω$\textrm{cm}^2$ specific resistance were observed indicating low loss thermal emission and tunneling processes over and through the potential barrier. Current-voltage (I-V) characteristics in p$^{+}$Ge/pSi structures show rectifying properties for room temperature bonded structures. After annealing at 40$0^{\circ}C$, the potential barrier was reduced and the barrier height no longer blocks current flow under bias. From these observations, interfacial atomic bonding structures of hydrophobically wafer bonded Ge/Si heterostructures are suggested.ested.

• Korean Journal of Materials Research
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• v.4 no.4
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• pp.416-427
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• 1994

The changes of crystallinity and microstructure and the $Si_{1-x}Ge_x/Sio_2$ interfaces of $Si_{1-x}Ge_x$ alloys deposited on amorphous $SiO_{2}$ were studied as a function of deposition temperature. The crystallinity, microstructure, and compositional uniformity of $Si_{1-x}Ge_x$ alloys deposited on the SiOl at different temperature were investigated by X-ray diffraction and transmission electron microscopy. And $Si_{1-x}Ge_x/Sio_2$ interface were investigated by high-resolution transmission electron microscopy. The $Si_{0.7}Ge_{0.3}/Sio_2$ films were deposited on amorphous $SiO_{2}$ at $300^{\circ}C,400^{\circ}C,500^{\circ}C,600^{\circ}C,$ and $700^{\circ}C$ by Si-MBE. In the film deposited at $300^{\circ}C$, only amorphous phase were observed. In the film deposited at $400^{\circ}C$, both amorphous and polycrystalline films were observed. Both phases were deposited simultaneously, but, at initial film growth, amorphous phase prevailed over polycrystalline phase. As the film thickness increased, the fraction of polycrystalline phase increased. At $500^{\circ}C$, thin amorphous layer was observed at lOnm from $SiO_{2}$ surface. In the films deposited at higher than $600^{\circ}C$, only crystalline phase were observed. Polycrystalline films had columnar structure. Compositional uniformity for deposited films were good regardless of deposition temperature. The interfaces of $Si_{1-x}Ge_x/Sio_2$ were flat, whatever polycrystal or amorphous was deposited on $SiO_{2}$.