• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.12
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• pp.1080-1086
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• 2005

We have studied the Ge redistribution after dry oxidation and the oxide growth rate of $Si_{1-x}Ge_x$ epitaxial layer. Oxidation were performed at 700, 800, 900, and $1,000\;^{\circ}C$. After the oxidation, the results of RBS (Rutherford Back Scattering) & AES(Auger Electron Spectroscopy) showed that Ge was completely rejected out of the oxide and pile up at $Si_{1-x}Ge_x$ interface. It is shown that the presence of Ge at the $Si_{1-x}Ge_x$ interface changes the dry oxidation rate. The dry oxidation rate was equal to that of pure Si regardless of Ge mole fraction at 700 and 800$^{\circ}C$, while it was decreased at both 900 and $1,000^{\circ}C$ as the Ge mole fraction was increased. The dry of idation rates were reduced for heavy Ge concentration, and large oxiidation time. In the parabolic growth region of $Si_{1-x}Ge_x$ oxidation, the parabolic rate constant are decreased due to the presence of Ge-rich layer. After the longer oxidation at the $1,000^{\circ}C$, AES showed that Ge peak distribution at the $Si_{1-x}Ge_x$ interface reduced by interdiffusion of silicon and germanium.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.449-452
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• 1998

We have studied the oxidatio nrte of $Si_{1-x}Ge_{x}$ epitaxial layer grown by MBE(molecular beam epitaxy). Oxidation were performed at 700.deg. C, 800.deg. C, 900.deg. C, and 1000.deg. C. After the oxidation, the results of AES(auger electron spectroscopy) showed that Ge was completely rejected out of the oxide and pile up at $SiO_{2}/$Si_{1-x}Ge_{x}$ interface. It is shown that the presence of Ge at the $SiO_{2}$/$Si_{1-x}Ge_{x}$ interface changes the dry oxidation rate. The dry oxidation rate was equal to that of pure Si regardless of Ge mole fraction at 700.deg. C and 800.deg.C, while it was decreased at both 900.deg. C and 1000.deg.C as the Ge mole fraction was increased. The ry oxidation rates were reduced for heavy Ge concentration, and large oxidation time. In the parabolic growth region of $Si_{1-x}Ge_{x}$ oxidation, The parabolic rate constant are decreased due to the presence of Ge-rich layer. After the longer oxidation at the 1000.deg.C, AES showed that Ge peak distribution at the $SiO_{2}$/$Si_{1-x}Ge_{x}$ interface reduced by interdiffusion of silicon and germanium.

• Korean Journal of Materials Research
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• v.19 no.12
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• pp.699-702
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• 2009

Due to the importance of the SiGe/Si heterostructure in the fields of thermoelectric and electronic applications, SiGe/Si heterostructures have been extensively investigated. For practical applications, thermal stability of the heterostructure during the thermoelectric power generation or fabrication process of electronic devices is of great concern. In this work, we focused on the effect of thermal annealing on the defect configuration in the SiGe/Si heterostructure. The formation mechanism of planar defects in an annealed SiGe/Si heterostructure was investigated by transmission electron microscopy. Due to the interdiffusion of Si and Ge, interface migration phenomena were observed in annealed heterostructures. Because of the strain gradient in the migrated region between the original interface and the migrated interface, the glide of misfit dislocation was observed in the region and planar defects were produced by the interaction of the gliding misfit dislocations. The planar defects were confined to the migrated region, and dislocation pileup by strain gradient was the origin of the confinement of the planar defect.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.6
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• pp.448-453
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• 2019

This work reports the electrical characteristics of and temperature distribution in chalcogenide phase change memory (PCM) devices that have a self-aligned structure. GST (Ge-Sb-Te) chalcogenide alloy films were formed in a self-aligned manner by interdiffusion between sputter-deposited Ge and $Sb_2Te_3$ films during thermal annealing. A transmission electron microscopy-energy dispersive X-ray spectroscopy (TEM-EDS) analysis demonstrated that the local composition of the GST alloy differed significantly and that a $Ge_2Sb_2Te_5$ intermediate layer was formed near the $Ge/Sb_2Te_3$ interface. The programming current and threshold switching voltage of the PCM device were much smaller than those of a control device; this implies that a phase transition occurred only in the $Ge_2Sb_2Te_5$ intermediate layer and not in the entire thickness of the GST alloy. It was confirmed by computer simulation, that the localized phase transition and heat loss suppression of the GST alloy promoted a temperature rise in the PCM device.