• Nuclear Engineering and Technology
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• v.39 no.2
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• pp.123-128
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• 2007

In order to apply a static fault-tree (FT) method to a system or a plant whose configuration changes dynamically, condition gates and a post processing method are used to effectively accommodate these changes. An operator's performance change, which can be caused by these configuration changes, should also be considered to assess the risk to a plant in a more realistic manner. This study aims to develop an integrated framework to accommodate various configuration changes and their effect on an operator’s performance by using the FT model. We applied a condition-based human reliability assessment (CBHRA) method to consider various conditions endured by an operator. That is, we integrated the CBHRA method with the conventional post processing method for modeling the system configuration changes. The effect of the condition monitoring systems installed in a plant is also considered. In this study, we show an example application of the integrated framework to a probabilistic safety assessment for the shutdown phase of a nuclear power plant.

• ETRI Journal
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• v.43 no.4
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• pp.728-745
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• 2021

Carbon nanotube field-effect transistors (CNTFETs) have been widely studied as a promising technology to be included in post-complementary metal-oxide-semiconductor integrated circuits. Despite significant advantages in terms of delay and power dissipation, the fabrication process for CNTFETs is plagued by fault occurrences. Therefore, developing a fast and accurate method for estimating the reliability of CNTFET-based digital circuits was the main goal of this study. In the proposed method, effects related to faults that occur in a gate's transistors are first represented as a probability transfer matrix. Next, the target circuit's graph is traversed in topological order and the reliabilities of the circuit's gates are computed. The accuracy of this method (less than 3% reliability estimation error) was verified through various simulations on the ISCAS 85 benchmark circuits. The proposed method outperforms previous methods in terms of both accuracy and computational complexity.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.1
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• pp.47-56
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• 1999

As the density of logic gates of VLSI chips has rapidly increased, more number of I/O pins has been required. This results in bigger package size and higher packager cost. The package cost is higher than the cost of bare chips for high I/O count VLSI chips. As the density of logic gates increases, the reduction method of the number of I/O pins for a given complexity of logic gates is required. In this paper, we propose the novel I/O interface circuit using CTR (Constant-Transition-Rate) code to reduce 50% of the number of I/O pins. The rising and falling edges of the symbol pulse of CTR codes contain 2-bit digital data, respectively. Since each symbol of the proposed CTR codes contains 4-bit digital data, the symbol rate can be reduced by the factor of 2 compared with the conventional I/O interface circuit. Also, the simultaneous switching noise(SSN) can be reduced because the transition rate is constant and the transition point of the symbols is widely distributed. The channel encoder is implemented only logic circuits and the circuit of the channel decoder is designed using the over-sampling method. The proper operation of the designed I/O interface circuit was verified using. HSPICE simulation with 0.6 m CMOS SPICE parameters. The simulation results indicate that the data transmission rate of the proposed circuit using 0.6 m CMOS technology is more than 200 Mbps/pin. We implemented the proposed circuit using Altera's FPGA and confimed the operation with the data transfer rate of 22.5 Mbps/pin.

• Restorative Dentistry and Endodontics
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• v.24 no.2
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• pp.337-345
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• 1999

The purpose of this study was to compare the shape of root canal after instrumentation with some engine driven NiTi files. Thirty narrow and curved canals(15-35 degree) of mesial canals of extracted human mandibular first molars were divided into three groups. Group 1: After radicular access with Gates Glidden drill, apical shaping using step back method with Flexo file Group 2: After radicular access with Gates Glidden drill, apical shaping with Profile .04 Group 3: Canal shaping with GT file and Profile .04. Using modified Bramante technique, the root was sectioned at 2 mm from apical foramen, height of curvature, 2 mm from canal orifice. Canal centering ratio, amount of transport, amount of dentin removed, shape of canal were measured and statistical analysis is done using SPSS Program V 7.5. The results were as follows: 1. Canal centering ratio of group 3 was the lowest at coronal part, but there was no statistical difference. Centering ratio of group 2 was the lowest at curve part, and there was statistical difference between group 1(P<0.05). Centering ratio of group 2 was the lowest at apical part, but there was no statistic difference. 2. Amount of transport of group 3 was the lowest at coronal part, but there was no statistical difference. Amount of transport of group 2 was the lowest at curve part, and there was statistical difference between group 1(P<0.05). Amount of transport of group 3 was the lowest at apical part, and there was statistical difference between group 1 and group 2, group 1 and group 3(P<0.05). 3. Amount of dentin removed of group 3 was the lowest at coronal part, bur there was no statistical difference. Amount of dentin removed of group 2 was the lowest at curve part, but there was no statistical difference. Amount of dentin removed or group 2 was the lowest at apical part, and there was statistical difference between group 1 and group 2, group 1 and group 3(P<0.05). 4. The shape of the canals after instrumentation varied among the groups. The majority of canals at coronal and curve part for group 1 were round in shape(7 in 10), those at apical part were oval(8 in 10). The majority of canals at coronal part for group 2 were round in shape(7 in 10) and there was no difference in the number of shape at other part. There was no difference in the number of shape at every part for group 3. As above results, NiTi rotary instrumentation showed a trend to remain more centered in the canal than SS file instrumentation. At using NiTi file, coronal shaping with Gates Glidden drill was not statistically different from shaping with GT file. But shaping with GT file showed tapered canals, so it may be said that shaping with GT file is a safe and valuable instrumentation method.

• Journal of Practical Engineering Education
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• v.16 no.3_spc
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• pp.391-399
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• 2024

All highway toll gates in Korea use low-speed WIM(Weight-In-Motion) to block overloaded cargo vehicles from entering the main highway, but some cargo vehicle owners are illegally modifying vehicles to operate variable axles and evading crackdowns by manipulating the axles. In previous studies detect all tires of a running vehicle were detected to determine whether there is axle manipulation. However, because the vehicle entry area at the highway toll gate checkpoint is very narrow, there is a problem that it is realistically difficult to film all tires of the entering vehicle in one video frame. In this paper, we proposed a system that can determine whether the axle is being operated through changes in the height of the vehicle's cargo box rather than by detecting tires. To detect changes in the height of a cargo box, we propose a method to extract the representative line of the cargo box using Hough transform and then measure the change in height of the representative line to detect the change in height of the cargo box. In addition, we propose a method to detect changes in the vertical height of a cargo box by accumulating motion vectors of pixels within a certain area of the image using optical flow. And the two methods were compared and their advantages and disadvantages were analyzed and presented.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.2
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• pp.56-63
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• 2011

This paper presents the method of giving hysteresis characteristics to the digital input port of microprocessors or micro-controllers and it's design procedures. And this paper shows the example of circuit design and the effect of this method by experiments. Presented method has advantages : By the additional one port and two resistors, input port can have hysteresis characteristics and hysteresis band is larger than TTL, CMOS schmitt trigger gates.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.5
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• pp.411-421
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• 1988

This paper offers a method to design CCD four-valued circuits using the tabular method. First, the four-valued logic function is decomposed by hand-calculation or computer program. Nest, the algorithm is derived form the tabular method based on the decomposition process to realize the DDC four-valued circuit. According to this algorithm, the two-variable four valued logic function is decomposed and realized by CCD network with four basic gates. The synthesis method in this paper proves that the number of devices and cost is considerably reduces as compared with the existing methods to realize the same logic functions.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.6
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• pp.63-70
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• 1994

In this paper, we propose a fault simulation method based on primary output in combinational circuit. In the deterministic test pattern generation, each test pattern is genterated incrementally. The test pattern is applied to the primary inputs of circuit under test to simulate faults. We detect the faults with respect to each primary output. The fault detection with resptect to each primary output is reflected by the corresponding bit in the detection words, and efficient fault detection for the reconvergent fan-out stem is achieved with dynamic fault propagation. As an experimental result of the fault simulation with our method for the several bench mark circuits, we illustrated the good performance showing that the number of gates to be activated is much reduced as compared with other method which is not based on primary output.

• Journal of Korean Port Research
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• v.13 no.1
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• pp.133-146
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• 1999

Mokpo coastal area is connected to the adjacent a long river and two large basins. It is essential for port planning coastal zone management and environmental impact study to analyze the data related to the ship operation and variation of current and water quality due to the development of water area including dredging reclamation and estuary barrage. The Yongsan river estuary weir and Yongam-Kumho basins discharge much of water through water gates for the purpose of flood control and prohibit salt intrusion at the inland fresh water area. To meet this purpose discharge through the gates have been done at the period of maximum water level difference between inner river and sea level. This discharged water may cause the changes of current pattern and other environmental influences in the vicinity and inner area of semi-closed Mokpo harbor. In this study ADI method is applied to the governing equation for the analysis of the changes on current pattern due to discharged water. As the results of this study it is known that the discharging operation causes many changes including the increase of current velocity at the front water area at piers approaching passage and anchorages. Discussion made on the point of problems such as restricted maneuverability and the safety of morred vessels at pier and anchorage. To minimize this influence the linked gate operation discharging warning system and laternative mooring system are recommended.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.11
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• pp.1233-1240
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• 2014

For the last three decades after the advent of the Toffoli gate in 1980, while many reversible circuit syntheses have been presented reversible embedding methods onto suitable reversible functions, only a few proposed direct irreversible-to-reversible mapping methods without reversible embedding. In this paper we present two effective policies to reduce the gate cost and complexity for the existing direct reversible mapping methods without reversible embedding. In order to develop new cost reduction policies we consider the cost influence of Toffoli module according to NOT gate arrangement in classical circuits. From this we deduced an inverse proportional property between inverting input numbers of classical AND/OR gates and reversible Toffoli module cost based on a fact - the inverting inputs of classical AND(OR) gates increase(decrease) the Toffoli module cost. We confirm the applications of the inverting input rearrangement and maximum fan-out policies preceding direct reversible mapping will be effective method to improve the reversible Toffoli module cost and complexity with the parallel using of the fan-out and supercell ones.