• Title/Summary/Keyword: Gates' method

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ASIC Design of Frame Sync Algorithm Using Memory for Wireless ATM (무선 ATM망에서 메모리를 이용한 프레임 동기 알고리즘의 ASIC 설계)

  • 황상철;김종원
    • Proceedings of the IEEK Conference
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    • 1998.06a
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    • pp.82-85
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    • 1998
  • Because ATM was originally designed for the optical fiber environment with bit error rate(BER) of 10-11, it is difficult to maintain ATM cell extraction capability in wireless environment where BER ranges from 10-6 to 10-3. Therefore, it must be proposed the algorithm of ATM cell extraction in wereless environment. In this paper, the frame structure and synchronization algorithm satisfyling the above condition are explained, and the new ASIC implementation method of this algorithm is proposed. The known method using shift register needs so many gates that it is not suitable for ASIC implementation. But in the proposed method, a considerable reduction in gate count can be achieved by using random access memory.

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Construction of Combinational MVL Function Based on T-Gate Integrated Module (T-게이트 통합 모듈에 의한 조합 MVL 함수의 구성)

  • 박동영;최재석;김흥수
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.26 no.11
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    • pp.1839-1849
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    • 1989
  • An optimal variable assignment algorithm is presented as a decomposition method of MVL functions. A given 3-valued combinational logic function is disintegrated into subfunction composed of the function dependant relation, then extracted implicant output elements from subfunctions are assigned to a T-gates. As a circuit implementation tool, a programmable integarated T-gate module is proposed, and the construction procedure of combinational MVL functions is systematized in each step. This method is expected to give properties of the systematic procedure, possibility of T-gate number reduction, unification of module, and flexibility of module composition. Specially variable decomposition method can be pointed out as an approach to solving the limitation problem of the input and output terminal number in VLSI implementations.

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Nanoscale NAND SONOS memory devices including a Seperated double-gate FinFET structure

  • Kim, Hyun-Joo;Kim, Kyeong-Rok;Kwack, Kae-Dal
    • Journal of Applied Reliability
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    • v.10 no.1
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    • pp.65-71
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    • 2010
  • NAND-type SONOS with a separated double-gate FinFET structure (SDF-Fin SONOS) flash memory devices are proposed to reduce the unit cell size of the memory device and increase the memory density in comparison with conventional non volatile memory devices. The proposed memory device consists of a pair of control gates separated along the direction of the Fin width. There are two unique alternative technologies in this study. One is a channel doping method and the other is an oxide thickness variation method, which are used to operate the SDF-Fin SONOS memory device as two-bit. The fabrication processes and the device characteristics are simulated by using technology comuter-adided(TCAD). The simulation results indicate that the charge trap probability depends on the different channel doping concentration and the tunneling oxide thickness. The proposed SDG-Fin SONOS memory devices hold promise for potential application.

A ASIC design of the Improved PN Code Acquisition System for DS/CDMA (DS-CDMA용 개선된 PN 코드 포착 시스템의 ASIC 설계)

  • Jo, Byeong-Rok;Park, Jong-U
    • The KIPS Transactions:PartD
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    • v.9D no.1
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    • pp.161-166
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    • 2002
  • The existing method in PN code acquisition process have a problem in PN code acquisition time because PN code searching is accomplished in one epoch. In this paper, we propose algorithm that can reduce PN code acquisition time because PN code searching is accomplished in each other two epoches. The designed ASIC chip using proposed algorithm confirmed that the area (the number of gates) increase more than existing method in PN code acquisition, but the performance of PN code acquisition is better than existing method.

Performance Analysis of Detector in Automobile Pulse Radar with Considering Interference (차량용 펄스 레이더에서 간섭영향에 대한 검출기의 성능 분석)

  • Lee, Jonghun;Ko, Seokjun
    • IEMEK Journal of Embedded Systems and Applications
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    • v.14 no.1
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    • pp.11-18
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    • 2019
  • In this paper, we consider interferences from other automobile pulse radars using same frequency spectrum. In order to eliminate the interference, we propose the PN code modulation method. This method uses the cross-correlation between PN codes with different seed. The ROC performance is used for comparing the proposed detector to conventional method. And the proposed detector can decide the present or absent of targets and measure the range of the targets by using memory buffer of range gate. Especially, we use false alarm probability for all range gates. That is the false alarm if in any one range gate the false alarm occurs. From the simulation result, we can see that the proposed detector with using PN code is not influenced by interferences.

Suitability of Measuring a Kidney Depth with Assessment of Glomerular Filtration Rateusing 99mTc-DTPA in the Ectopic Kidney and Pediatric Patients (99mTc-DTPA를 이용한 사구체여과율 검사에서 이소성 신장과 소아 환자의 신장 깊이 측정방법의 적절성)

  • Choi, Jae Min;Lee, Young Hee;Shim, Dong Oh
    • The Korean Journal of Nuclear Medicine Technology
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    • v.18 no.2
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    • pp.62-67
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    • 2014
  • A glomerular filtration rate (GFR) study is a test that uses radioactive materials or tracers (radiopharmaceuticals) and a computer to see how well the kidneys are working. Asan Medical Center analyzed and compared data between kidney depth, acquired from kidney donors' CT image and acquired from Gates method's GFR value that are calculated by Tonnesen equation. This study was able to confirm that kidney depth measured from CT image was higher than the Gates Method's GFR value, which was calculated by Tonnessen equation; the direct relationship among pathologic results is confirmed. Particularly, kidney donor whose kidney was at the pelvic area had direct relationship with other clinical results. During the GFR test, it is necessary to confirm the location of kidney has no change with reference of CT image. If kidney depth is manually corrected using CT image when we measures GFR of deformed or horse-shoe kidney, it would be possible to acquire the compatible value which is equivalent to clinical result. There would be a possible issue of appropriateness that whether the applied GFR using CT image's kidney depth has clinical validity. In case of a pediatric patient, the GFR derived from Tonnesen was quiet underestimated while manual method and Gordon stay in normal range. Which results may be correct among them? There have been many reports about kidney depth, to be an accurate index of GFR in children. As one of the study performers, we should contemplate what the best option for pediatric patients would be.

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Comparison of Activity Capacity Change and GFR Value Change According to Matrix Size during 99mTc-DTPA Renal Dynamic Scan (99mTc-DTPA 신장 동적 검사(Renal Dynamic Scan) 시 동위원소 용량 변화와 Matrix Size 변경에 따른 사구체 여과율(Glomerular Filtration Rate, GFR) 수치 변화 비교)

  • Kim, Hyeon;Do, Yong-Ho;Kim, Jae-Il;Choi, Hyeon-Jun;Woo, Jae-Ryong;Bak, Chan-Rok;Ha, Tae-Hwan
    • The Korean Journal of Nuclear Medicine Technology
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    • v.24 no.1
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    • pp.27-32
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    • 2020
  • Purpose Glomerular Filtration Rate(GFR) is an important indicator for evaluating renal function and monitoring the progress of renal disease. Currently, the method of measuring GFR in clinical trials by using serum creatinine value and 99mTc-DTPA(diethylenetriamine pentaacetic acid) renal dynamic scan is still useful. After the Gates method of formula was announced, when 99mTc-DTPA Renal dynamic scan is taken, it is applied the GFR is measured using a gamma camera. The purpose of this paper is to measure the GFR by applying the Gates method of formula. It is according to effect activity and matrix size that is related in the GFR. Materials and Methods Data from 5 adult patients (patient age = 62 ± 5, 3 males, 2 females) who had been examined 99mTc-DTPA Renal dynamic scan were analyzed. A dynamic image was obtained for 21 minutes after instantaneous injection of 99mTc-DTPA 15 mCi into the patient's vein. To evaluate the glomerular filtration rate according to changes in activity and matrix size, total counts were measured after setting regions of interest in both kidneys and tissues in 2-3 minutes. The distance from detector to the table was maintained at 30cm, and the capacity of the pre-syringe (PR) was set to 15, 20, 25, 30 mCi, and each the capacity of post-syringe (PO) was 1, 5, 10, 15 mCi is set to evaluate the activity change. And then, each matrix size was changed to 32 × 32, 64 × 64, 128 × 128, 256 × 256, 512 × 512, and 1024 × 1024 to compare and to evaluate the values. Results As the activity increased in matrix size, the difference in GFR gradually decreased from 52.95% at the maximum to 16.67% at the minimum. The GFR value according to the change of matrix size was similar to 2.4%, 0.2%, 0.2% of difference when changing from 128 to 256, 256 to 512, and 512 to 1024, but 54.3% of difference when changing from 32 to 64 and 39.43% of difference when changing from 64 to 128. Finally, based on the presently used protocol, 256 × 256, PR 15 mCi and PO 1 mCi, the GFR value was the largest difference with 82% in PR 15 mCi and PO 1 mCi. conditions, and at the least difference is 0.2% in the conditions of PR 30 mCi and PO 15 mCi. Conclusion Through this paper, it was confirmed that when measuring the GFR using the gate method in the 99mTc-DTPA renal dynamic scan. The GFR was affected by activity and matrix size changes. Therefore, it is considered that when taking the 99mTc-DTPA renal dynamic scan, is should be careful by applying appropriate parameters when calculating GFR in the every hospital.

A Study on the New Discharge AND Gate and Drive Scheme for the Cost Down of the PDPs (PDP의 가격절감을 위한 새로운 방전 AND Gate 및 구동기술에 관한 연구)

  • 염정덕
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.52 no.6
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    • pp.267-273
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    • 2003
  • The plasma display panel with the electrode structure of new discharge AND gate and its driving scheme were proposed and the driving system for experiment was developed. And operation of these discharge AND gate was verified by the experiment of PDP addressing with floating electrode. This discharge AND gate operated by the operation speed of 8$mutextrm{s}$ and the operation margin of 100V. The address operation margin of 10V also obtained. It was known to be able to control the discharge of the adjoining scan electrode accurately. Because proposed method uses the DC discharge the control of the discharge can be facilitated compared with conventional discharge AND gate. Moreover, because the input discharge and the output discharge of discharge gate are separate, the display discharge can be prevented from passing discharge gates. Therefore, it is possible to apply to the large screen plasma display panel. And the decrease of contrast ratio does not occur because the scanning discharge does not influence the picture quality.

Logic Circuit Fault Models Detectable by Neural Network Diagnosis

  • Tatsumi, Hisayuki;Murai, Yasuyuki;Tsuji, Hiroyuki;Tokumasu, Shinji;Miyakawa, Masahiro
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 2003.09a
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    • pp.154-157
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    • 2003
  • In order for testing faults of combinatorial logic circuit, the authors have developed a new diagnosis method: "Neural Network (NN) fault diagnosis", based on fm error back propagation functions. This method has proved the capability to test gate faults of wider range including so called SSA (single stuck-at) faults, without assuming neither any set of test data nor diagnosis dictionaries. In this paper, it is further shown that what kind of fault models can be detected in the NN fault diagnosis, and the simply modified one can extend to test delay faults, e.g. logic hazard as long as the delays are confined to those due to gates, not to signal lines.

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One-time Traversal Algorithm to Search Modules in a Fault Tree for the Risk Analysis of Safety-critical Systems (안전필수 계통의 리스크 평가를 위한 일회 순회 고장수목 모듈 검색 알고리즘)

  • Jung, Woo Sik
    • Journal of the Korean Society of Safety
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    • v.30 no.3
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    • pp.100-106
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    • 2015
  • A module or independent subtree is a part of a fault tree whose child gates or basic events are not repeated in the remaining part of the fault tree. Modules are necessarily employed in order to reduce the computational costs of fault tree quantification. This quantification generates fault tree solutions such as minimal cut sets, minimal path sets, or binary decision diagrams (BDDs), and then, calculates top event probability and importance measures. This paper presents a new linear time algorithm to detect modules of large fault trees. It is shown through benchmark tests that the new method proposed in this study can very quickly detect the modules of a huge fault tree. It is recommended that this method be implemented into fault tree solvers for efficient probabilistic safety assessment (PSA) of nuclear power plants.