• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.8-15
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• 2009

Side-channel attacks including the differential power analysis attack are often more powerful than classical cryptanalysis and have to be seriously considered by cryptographic algorithm's implementers. Various countermeasures have been proposed against such attacks. In this paper, we deal with the masking method, which is known to be a very effective countermeasure against the differential power analysis attack and propose new gate-level conversion methods between Boolean and arithmetic masks. The new methods require only 6n-5 XOR and 2n-2 AND gates with 3n-2 gate delay for converting n-bit masks. The basic idea of the proposed methods is that the carry and the sum bits in the ripple adder are manipulated in a way that the adversary cannot detect the relation between these bits and the original raw data. Since the proposed methods use only bitwise operations, they are especially useful for DPA-securely implementing cryptographic algorithms in hardware which use both Boolean and arithmetic operations. For example, we applied them to securely implement the block encryption algorithm SEED in hardware and present its detailed implementation result.

• Journal of architectural history
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• v.1 no.2 s.2
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• pp.68-84
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• 1992

The development of Buddhist architectures of the Unified Silla period have been generally understood to have paired pagoda instead of one which had been popular until before the unification. Besides the stylistic categorization of paired pagoda system, there had been no further investigation reported concerning whether there was any detailed process of change within the development of paired pagoda style. This paper aims to identify such change inside the development of paired pagoda style, which, externally, seems to be the same pattern of site design maintained throughout the period of Unified Silla that lasted for about three centuries. Since the temple sites of study are in the same pattern of layout, the method of investigation has to be such that can identify the subtle changes that, in external appearance, are not easily discernible. Hence, this research compared the dimensions of important measurement of five temple sites to be able to clarify the process of minor changes. Among many sites of Silla temples, only five were suitable for the research since detailed measurement were possible through field research or the report of excavation. They are the sites of Sachonwang-sa, Mangduk-sa, site of Kunsuri, and Bulguk-sa. Although the five sites have the same style of paired pagoda, it is clear that there were consistant flow of change. Even though the motivation of such change were not strong enough to change the site pattern itself, it resulted continuous minor changes such as the size and location of architectures. The size of image hall, for example, was growing larger and larger as time goes on, while, the size of Pagoda was getting smaller. In the same way, the size of middle gate became smaller while the size of lecture hall became larger, although the rate of change in these cases were not as severe as that of image hall and pagoda. At the same time, pagoda was coming closer to the middle gate leaving larger space in front of the image hall. Such aspect is even more meaningful considering the fact that the pagoda, from the 8th century in Japan and China, moved outside of the major precinct. The image hall, too, moved toward the middle gate slightly so that the space in front of the lecture hall became more spacious. Such changes, of course, were not accidental but they are the same continuous motivation of change that caused the changes before the period of unification. Enlargement of image hall and reduction of pagoda, for example, represent the changing relative importance of religious meaning. Hence, it is evident that one can not easily imterprete the development of one style only by categorizing it to be one same style. In the veiwpoint of the underlying motivation of change, the fact that one style persisted for a certain period of time, does not mean there had been no change, but means that it was the time of motivational accumulation, causing minor changes within the same style, to be able to create major change coming after.

• The Journal of the Korea Contents Association
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• v.10 no.6
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• pp.72-79
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• 2010

In this paper, we propose the data cache architecture with a write buffer for a 32bit asynchronous embedded processor. The data cache consists of CAM and data memory. It accelerates data up lood cycle between the processor and the main memory that improves processor performance. The proposed data cache has 8 KB cache memory. The cache uses the 4-way set associative mapping with line size of 4 words (16 bytes) and pseudo LRU replacement algorithm for data replacement in the memory. Dirty register and write buffer is used for write policy of the cache. The designed data cache is synthesized to a gate level design using $0.13-{\mu}m$ process. Its average hit rate is 94%. And the system performance has been improved by 46.53%. The proposed data cache with write buffer is very suitable for a 32-bit asynchronous processor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.90-97
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• 2006

In this paper, we present a cost-effective architecture of high-speed soft-decision Viterbi decoder for Multi-band OFDM(MB-OFDM) systems. In the design of modem for MB-OFDM systems, a parallel processing architecture is general]y used for the reliable hardware implementation, because the systems should support a very high-speed data rate of at most 480Mbps. A Viterbi decoder also should be designed by using a parallel processing structure and support a very high-speed data rate. Therefore, we present a optimized hardware architecture for 4-way parallel processing Viterbi decoder in this paper. In order to optimize the hardware of Viterbi decoder, we compare and analyze various ACS architectures and find the optimal one among them with respect to hardware complexity and operating frequency The Viterbi decoder with a optimal hardware architecture is designed and verified by using Verilog HDL, and synthesized into gate-level circuits with TSMC 0.13um library. In the synthesis results, we find that the Viterbi decoder contains about 280K gates and works properly at the speed required in MB-OFDM systems.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.11
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• pp.2031-2038
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• 2008

A small-area and high-speed authentication/security processor (WUSB_Sec) IP is designed, which performs the 4-way handshake protocol for authentication between host and device, and data encryption/decryption of wireless USB system. The PRF-256 and PRF-64 are implemented by CCM (Counter mode with CBC-MAC) operation, and the CCM is designed with two AES (Advanced Encryption Standard) encryption coles working concurrently for parallel processing of CBC mode and CTR mode operations. The AES core that is an essential block of the WUSB_Sec processor is designed by applying composite field arithmetic on AF$(((2^2)^2)^2)$. Also, S-Box sharing between SubByte block and key scheduler block reduces the gate count by 10%. The designed WUSB_Sec processor has 25,000 gates and the estimated throughput rate is about 480Mbps at 120MHz clock frequency.

• Journal of Ecology and Environment
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• v.47 no.3
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• pp.63-74
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• 2023

Background: Comparing with the several types of infrastructures, linear infrastructures are known to facilitate the spread of undesirable species in ecosystems. Recently, some new man-made habitats (e.g., gravel pads of the high-voltage towers, solid wastes and sewage habitats) were established along the Deltaic Mediterranean coast of Egypt as a result of the construction of the E-W coastal international highway. The current study evaluates the floristic composition associated with the pads of high-voltage towers that had been constructed for stabilizing the power line towers in the North Nile Delta. Plant cover was measured for 22 randomly stand. Results: Eighty-four species were recorded, of which 35 are perennials (41.6%), 2 biennials (2.3%) and 47 annuals (56.0%) belonging to 23 families. The largest families were Asteraceae (16 species), Poaceae (15 species), Chenopodiaceae (12 species), and Fabaceae (7 species). Ten aliens (10.7%) out of the 84 species were recorded. Therophytes have the highest percentage (58%), followed by hemicryptophytes (14%), chamaephytes (11%). Six vegetation groups were recognized in the study area after the application of two way indicator species analysis (TWINSPAN), Arthrocnemum macrostachyum, Phragmites australis, and Mesembryanthemum nodiflorum have the highest presence percentage. Both of Salsola cyclophylla and Solanum villosum were recorded for the first time in North Nile Delta. Natural habitat had the highest α-diversity, but the lowest β-diversity (4.9, 15.4), while gravel pads had the reverse (2.7, 30.8). Some species which are native to the desert habitats (e.g., Rumex pictus, Salsola kali, and Carthamus tenuis) were able to invade the North Nile Delta. Conclusions: Habitat of gravel pads is an expressing form about the intense of disturbance in Deltaic Mediterranean coast of Egypt. More of efforts should be carried out to avoid more human disturbances that creating as ruderal habitats which open the gate to invasive species in the flora of North Nile Delta.

• Journal of Advanced Navigation Technology
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• v.10 no.2
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• pp.167-172
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• 2006

In this paper, the 25W power amplifier for UHF band radio transceiver has been designed and realized. The power amplifier was composed of drive, power amplifier and control stages. Feedback topology and coaxial line baluns were used for wide band operation. The VDMOS, which has reliable performance for linearity and efficiency, was used for power device and designed to operate as push-pull amplification at Class AB Bias. The power amplifier designed in such a way was found to show stable AM modulation performance when voice signal was detected at the gate stage, with being designed and realized to meet output specifications of commercial air traffic control transmitter.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.758-761
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• 2004

This paper proposes a design and implementation of multiplierless digital PID (Proportional-Integral-Derivative) controller using FPGA (Field Programmable Gate Array) for controlling the speed of DC motor in digital system. The multiplierless PID structure is based on Distributed Arithmetic (DA). The DA is an efficient way to compute an inner product using partial products, each can be obtained by using look-up table. The PID controller is designed using MATLAB program to generate a set of coefficients associated with a desired controller characteristics. The controller coefficients are then included in VHDL (Very high speed integrated circuit Hardware Description Language) that implements the PID controller onto FPGA. MATLAB program is used to activate the PID controller, calculate and plot the time response of the control system. In addition, the hardware implementation uses VHDL and synthesis using FLEX10K Altera FPGA as target technology and use MAX+plusII program for overall development. Results in design are shown the speed performance and used area of FPGA. Finally, the experimental results can be shown when compared with the simulation results from MATLAB.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.6
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• pp.2483-2503
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• 2016

Traffic congestion is a severe problem in many modern cities around the world. Real-time and accurate traffic congestion identification can provide the advanced traffic management systems with a reliable basis to take measurements. The most used data sources for traffic congestion are loop detector, GPS data, and video surveillance. Video based traffic monitoring systems have gained much attention due to their enormous advantages, such as low cost, flexibility to redesign the system and providing a rich information source for human understanding. In general, most existing video based systems for monitoring road traffic rely on stationary cameras and multiple vehicle tracking method. However, most commonly used multiple vehicle tracking methods are lack of effective track initiation schemes. Based on the motion of the vehicle usually obeys constant velocity model, a novel vehicle recognition method is proposed. The state of recognized vehicle is sent to the GM-PHD filter as birth target. In this way, we relieve the insensitive of GM-PHD filter for new entering vehicle. Combining with the advanced vehicle detection and data association techniques, this multiple vehicle tracking method is used to identify traffic congestion. It can be implemented in real-time with high accuracy and robustness. The advantages of our proposed method are validated on four real traffic data.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.200-200
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• 2003

Polycrystalline Si(polysilicon) TFTs have opened a way for the next generation of display devices, due to their higher mobility of charge carriers relative to a-Si TFTs. The polysilicon W applications extend from the current Liquid Crystal Displays to the next generation Organic Light Emitting Diodes (OLED) displays. In particular, the OLED devices require a stricter control of properties of gate oxide layer, polysilicon layer, and their interface. The polysilicon layer is generally obtained by annealing thin film a-Si layer using techniques such as solid phase crystallization and excimer laser annealing. Typically laser-crystallized Si films have grain sizes of less than 1 micron, and their electrical/dielectric properties are strongly affected by the presence of grain boundaries. Impedance spectroscopy allows the frequency-dependent measurement of impedance and can be applied to inteface-controlled materials, resolving the respective contributions of grain boundaries, interfaces, and/or surface. Impedance spectroscopy was applied to laser-annealed Si thin films, using the electrodes which are designed specially for thin films. In order to understand the effect of grain size on physical properties, the amorphous Si was exposed to different laser energy densities, thereby varying the grain size of the resulting films. The microstructural characterization was carried out to accompany the electrical/dielectric properties obtained using the impedance spectroscopy, The correlation will be made between Si grain size and the corresponding electrical/dielectric properties. The ramifications will be discussed in conjunction with active-matrix thin film transistors for Active Matrix OLED.