• Journal of Korean Society for Quality Management
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• v.47 no.1
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• pp.151-162
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• 2019

Purpose: This study is in order to secure high quality of military supplies, it is important to secure design quality in the development phase. I will review how to establish a quality assurance system in the development phase based on the author's seminar presentation contents and application example of Hanwha Systems Co., Ltd. Methods: To guarantee design quality in the development phase, in 2002, quality assurance system that is adequate for SQA(Software Quality Assurance)'s requirements of CMM(Capability Maturity Model) was conduct. In 2009, based on the CMMI(Capability Maturity Model Integration) Level 5, there has been continuous and reenforced quality assurance activities. Results: By suggesting the construction and a case study on application of R&D quality assurance, it would be helpful for companies aiming to construct or enhance quality assurance system. Conclusion: To secure high quality for military supplies, a development QA system should be established to secure quality in the development phase. In addition, Total life cycle QA system for development, mass production and operation phase should be reestablished.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.11
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• pp.5389-5396
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• 2012

In this paper, an optimized residual data decoder architecture is proposed to improve the performance in H.264/AVC. The proposed architecture is an integrated architecture that combined parallel inverse transform architecture and parallel inverse quantization architecture with common operation units applied new inverse quantization equations. The equations without division operation can reduce execution time and quantity of operation for inverse quantization process. The common operation unit uses multiplier and left shifter for the equations. The inverse quantization architecture with four common operation units can reduce execution cycle of inverse quantization to one cycle. The inverse transform architecture consists of eight inverse transform operation units. Therefore, the architecture can reduce the execution cycle of inverse transform to one cycle. Because inverse quantization operation and inverse transform operation are concurrency, the execution cycle of inverse transform and inverse quantization operation for one $4{\times}4$ block is one cycle. The proposed architecture is synthesized using Magnachip 0.18um CMOS technology. The gate count and the critical path delay of the architecture are 21.9k and 5.5ns, respectively. The throughput of the architecture can achieve 2.89Gpixels/sec at the maximum clock frequency of 181MHz. As the result of measuring the performance of the proposed architecture using the extracted data from JM 9.4, the execution cycle of the proposed architecture is about 88.5% less than that of the existing designs.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.11
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• pp.27-32
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• 1999

Metal-ferroelectric-semiconductor devices by susing rapid thermal annealed $LiNbO_3/Si$(100) structures were fabricated and demonstrated nonvolatile memory operations. The estimated field-effect electron mobility and transconductance on a linear region of the fabricated FET were about $600cm^2/V{\cdot}s$ and 0.16mS/mm, respectively. The ID-VG characteristics of MFSFET's showed a hysteresis loop due to the ferroelectric nature of the $LiNbO_3 films. The drain current of the on state was more than 4 orders of magnitude larger than the off state current at the same read gate voltage of 0.5V, which means the memory operation of the MFSFET. A write voltage as low as ${\pm}3V$, which is applicable to low power integrated circuits, was used for polarization reversal. The ferroelectric capacitors showed no polarization degradation up to $10^{10}$ switching cycles with the application of symmetric bipolar voltage pulse (peak-to-peak 6V, 50% duty cycle) of 500kHz.

• Journal of IKEEE
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• v.19 no.4
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• pp.583-589
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• 2015

In the HEVC CABAC, the probability model is updated after a bin is encoded and next bin is encoded based on the updated probability model. Conventional CABAC encoders can encode only one bin per cycle, which cannot increase the encoding throughput. The probability model does not need to be updated in the bypass bins. In this paper, a HEVC CABAC encoder is proposed to increase encoding throughput by parallel processing of bypass bins. The designed CABAC encoder can process either a regular bin or maximum 4 bypass bins in a cycle. On the average, it can process 1.15~1.92 bins in a cycle. Synthesized in 0.18 um technology, its gate count, maximum operating speed, and the maximum throughput are 78,698 gates, 136 MHz, and 261 Mbin/s, respectively.

• Korean Journal of Materials Research
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• v.18 no.3
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• pp.148-152
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• 2008

A new cost-effective atomic layer deposition (ALD) technique, known as Proximity-Scan ALD (PS-ALD) was developed and its benefits were demonstrated by depositing $Al_2O_3$ and $HfO_2$ thin films using TMA and TEMAHf, respectively, as precursors. The system is consisted of two separate injectors for precursors and reactants that are placed near a heated substrate at a proximity of less than 1 cm. The bell-shaped injector chamber separated but close to the substrate forms a local chamber, maintaining higher pressure compared to the rest of chamber. Therefore, a system configuration with a rotating substrate gives the typical sequential deposition process of ALD under a continuous source flow without the need for gas switching. As the pressure required for the deposition is achieved in a small local volume, the need for an expensive metal organic (MO) source is reduced by a factor of approximately 100 concerning the volume ratio of local to total chambers. Under an optimized deposition condition, the deposition rates of $Al_2O_3$ and $HfO_2$ were $1.3\;{\AA}/cycle$ and $0.75\;{\AA}/cycle$, respectively, with dielectric constants of 9.4 and 23. A relatively short cycle time ($5{\sim}10\;sec$) due to the lack of the time-consuming "purging and pumping" process and the capability of multi-wafer processing of the proposed technology offer a very high through-put in addition to a lower cost.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.2
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• pp.329-334
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• 2014

This paper proposes the hardware architecture of high performance multi-mode 2D forward transform for HEVC which has same number of cycles for processing any type of four TUs and yield high throughput. In order to make the original image which has high pixel and high resolution into highly compressed image effectively, the transform technique of HEVC supports 4 kinds of pixel units, TUs and it finds the optimal mode after performs each transform computation. As the proposed transform engine uses the common computation operator which is produced by analyzing the relationship among transform matrix coefficients, it can process every 4 kinds of TU mode matrix operation with 35cycles equally. The proposed transform block was designed by Verilog HDL and synthesized by using TSMC 0.18um CMOS processing technology. From the results of logic synthesis, the maximum operating frequency was 400MHz and total gate count was 214k gates which has the throughput of 10-Gpels/cycle with the $4k(3840{\times}2160)@30fps$ image.

• Journal of IKEEE
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• v.18 no.3
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• pp.356-361
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• 2014

This paper proposes hardware architecture of HEVC (high efficiency video coding) CABAC (context-based adaptive binary arithmetic coding) binarizer. The proposed binarizer was designed and implemented as an independent module that can be integrated into HEVC CABAC encoder. It generates each bin string of each syntax element in a single cycle. It consists of controller module, TU (truncated unary binarization) module, TR (truncated Rice binarization) module, FL (fixed length binarization) module, EGK (k-th order exp-Golomb coding) module, CALR (coeff_abs_level_remaining) module, QP Delta (cu_qp_delta_abs) module, Intra Pred (intra_chroma_pred_mode) module, Inter Pred (inter_pred_idc) module, and Part Mode (part_mode) module. The proposed binarizer was designed in Verilog HDL, and it was implemented in 45 nm technology. Its operating speed, gate count, and power consumption are 200 MHz, 1,678 gates, and 50 uW, respectively.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.10a
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• pp.46-50
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• 2001

Due to its ability in producing a net-shape product to high precision in a very shot cycle time, injection molding has become one of the most important polymer-processings in the industry today. Recently the CAE applications in the field of injection molding have provided significant contributions to the mold design and process optimization. As a part of such an application the packing process has been studied using C-PARK. The prediction of pressure variations during post-filling stage for amorphous material has been compared with an experimental observation for a simple rectangular geometry of uniform thickness. And the optimal packing processes were calculated using the cavity pressure curve near the gate. As a case study, a warpage simulation was carried out for a DY-HOLDER with the variable number of gates.

• Journal of the Korean Society for Precision Engineering
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• v.20 no.11
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• pp.41-46
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• 2003

The objective of this paper is to present a methodology for automatically balancing multi-cavity injection molds with the aid of flow simulation. After the runner and cavity layout has been designed, the methodology adjusts runner and gate sizes iteratively based on the outputs of flow analysis. This methodology also ensures that the runner sizes in the final design are machinable. To illustrate this methodology, an example is used wherein a 3-cavity mold is modeled and filling of all the cavities at the same time is achieved. Based on the proposed methodology, a multicavity mold with identical cavities is balanced to minimize overall unfilled volume among various cavities at discrete time steps of the molding cycle. The example indicates that the described methodology can be used effectively to balance runner systems for multi-cavity molds.

• Applied Science and Convergence Technology
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• v.24 no.1
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• pp.16-21
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• 2015

The characteristics of an atmospheric pressure plasma jet (APPJ) in He discharge are measured with electrical and optical diagnostics methods. The discharge phenomenon in one cycle of the APPJ was diagnosed using intensified charge coupled device (ICCD) imaging. The gate mode images show that the propagation of plasma bullets happens only when the applied voltage on the inner conductor is positive. Moreover, the Schlieren image of the plasma jet shows that the laminar flow is changed into a turbulent flow when the plasma jet is turned on, especially when the gas flow rate increases.