• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 학술대회지
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• pp.612-615
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• 2004

A high-voltage generator is used to program the anti-fuse of the semiconductor chip. A new high-voltage generator consists of PN diodes and new stack type capacitors. An oscillator supply pulses to the high-voltage generator. The pulse period of the oscillator is delayed by controlling gate-voltage of the MOS. The pulse period is about 27ns, therefore the pulse frequency is about 37MHz. The threshold voltage of PN diode is about 0.8V. The capacitance of new stack type capacitor is about 4pF. The output voltage of the new high-voltage generator is about 7.9V and its current capacity is about $488{\mu}$A.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2005년도 추계학술대회 논문집
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• pp.671-675
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• 2005

In this paper, Development of propulsion system using IPM(Intelligent Power Module) for DC electric vehicle is proposed. Designed propulsion system is comprised of inverter stack which includes 6 IPM, BCH(Breaking Chopper) unit, FC(Filter Capacitor), Control unit. IPM can compose propulsion system simple by including gate drive circuit and protection circuit. Inverter stack is designed as a simple structure using IPM and non clamp capacitor. VVVF Inverter control is used the vector control strategy at low velocity region and slip frequency-control strategy at high velocity region. Designed propulsion system proves the performance through test and revenue service.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2007년도 추계학술대회 논문집
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• pp.118-119
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• 2007

Phase stability and morphological investigation on the $Si/SiO_2/HfO_2$ and $Si/SiO_2/ZrO_2$ stack are presented. Thermal stability of $HfO_2$ and $ZrO_2$ determines the quality of interface and subsequently the performance of device. The stacks have been fabricated and annealed at $1000^{\circ}C$ for various time. In evolution of crystalline phase and morphology (electrical and geometrical) of high-k materials, annealing time and process are observed to be crucial factors. The crystallization of some phase has been observed in the case of $Si/SiO_2/HfO_2$. The chemical environment around Zr and Hf in respective samples is observed to be different.

• 한국결정학회지
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• 제16권2호
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• pp.89-101
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• 2005

Among many material processing related issues for successful scaling down of devices for the next 10 years or so, the advanced gate stack and interconnect technology are two most critical research areas, which need technical innovation. The introduction of new metallic films and appropriate processing technologies are required more than ever. Especially, as the device downscaling continues well into sub 50 nm regime, the paradigm for metal nano film deposition technique research has been shifted to high conformality, low growth temperature, high quality with uniformity at large area wafers. Regarding these, ALD has sparked a lot of interests for a number of reasons. The process is intrinsically atomic in nature, resulting in the controlled deposition of films in sub-monolayer units with excellent conformality. In this paper, the overview on the current issues and the future trends in device processing technologies related to metal nano films as well as the R&D trends in these applications will be discussed. The focus will be on the applications for metal gate, capacitor electrode for DRAM, and diffusion barriers/seed layers for Cu interconnect technology.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 추계학술발표강연 및 논문개요집
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• pp.58-58
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• 2003

최근 전자재료분야 중 고집적 소자를 다루는 분야에서는 산화규소 유전박막의 두께가 얇아짐에 따라 상부전극과 하부기판 사이에서 발생하는 누설전류가 큰 문제가 되었다. 따라서 이를 극복하기 위해 고유전상수를 가진 두꺼운 유전박막을 사용하기 시작하였는데, 그 중 대표적 인 것이 하프늄옥사이드(HfO2)와 알루미나(A12O3)이다. HfO2의 장점은 큰 유전상수를 갖는다는 것이고, A1203의 장점은 열적 안정성 이 뛰어나며, 높은 bandgap에너지를 갖는 것인데, 이 둘의 장점을 살려서 보다 편리한 방법으로 박막을 증착한 것이 바로 HfAlO이다.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2002년도 추계학술대회 논문집(I)
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• pp.580-584
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• 2002

This paper proposes an experimental study on the traction system of rubber tired AGT (Automated Guideway Transit). IGBT VVVF inverter is developed for 1C2M propulsion system of AGT, and it consists of inverter stack, gate control unit, control unit, and interface unit. The combination test was carried out to prove the performance of inverter, and test results show that the developed inverter is excellent.

• 설비공학논문집
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• 제30권1호
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• pp.1-9
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• 2018

Thermal performance of a heat sink for an inverter power stack was analyzed in terms of array and installation location of an Insulated Gate Bipolar Transistor (IGBT). Thermal flow around the heat sink was calculated with a numerical model that could simulate forced convection. Thermal performance was calculated depending on the array and location of high- and low-power IGBTs considering the maximum temperature of IGBT. The optimum array and installation location were found and causes were analyzed based on results of numerical analysis. For the numerical analysis, experiment design considered the installation location of IGBT, ratio of heat generation rates of high- and low-power IGBTs, and velocity of the inlet air as design variables. Based on numerical results, a correlation that could calculate thermal performance of the heat sink was suggested and the maximum temperature of the IGBT could be predicted depending on the installation method.

• Journal of Power Electronics
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• 제16권2호
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• pp.786-797
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• 2016

This paper describes the design and development of a novel semiconductor-based solid-state switch for damped oscillating voltage test system. The proposed switch is configured as two identical series-connected switch stacks, each of which comprising 10 series-connected IGBT function units. Each unit consists of one IGBT, a gate driver, and an auxiliary voltage sharing circuit. A single switch stack can block 20 kV-rated high voltage, and two stacks in series are proven applicable to 30 kV-rated high voltage. The turn-on speed of the switch is approximately 250 ns. A flyback topology-based power supply system with a front-end power factor correction is built for the drive circuit by loosely inductively coupling each unit with a ferrite core to the primary side of a power generator to obtain the advantages of galvanic isolation and compact size. After the simulation, measurement, and estimation of the parasitic effect on the gate driver, a prototype is assembled and tested under different operating regimes. Experimental results are presented to demonstrate the performance of the developed prototype.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권2호
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• pp.68-73
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• 2006

We propose a damascene gate FinFET with Si nanocrystals implemented on bulk silicon wafer for low voltage flash memory device. The use of optimized SRON (Silicon-Rich Oxynitride) process allows a high degree of control of the Si excess in the oxide. The FinFET with Si nanocrystals shows high program/erase (P/E) speed, large $V_{TH}$ shifts over 2.5V at 12V/$10{\mu}s$ for program and -12V/1ms for erase, good retention time, and acceptable endurance characteristics. Si nanocrystal memory with damascene gate FinFET is a solution of gate stack and voltage scaling for future generations of flash memory device. Index Terms-FinFET, Si-nanocrystal, SRON(Si-Rich Oxynitride), flash memory device.

• 한국산학기술학회논문지
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• 제9권6호
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• pp.1726-1732
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• 2008

사출성형은 다양한 형태의 제품을 대량 생산할 수 있는 플라스틱 성형 공법중의 하나이다. 플라스틱 제품을 만들기 위해서는 고상의 재료를 액상으로 녹인 후 다시 고상으로 굳히는 과정을 거치는 데, 이 과정 중에 많은 문제점들이 발생을 하게 된다. 과거에는 이러한 문제를 해결하기 위해서 성형 후 금형 설계 변경 등의 시행착오적 방법을 사용하였으나, 성형과정에 대한 사출성형 CAE(Computer Aided Engineering)를 적용함으로써, 사전에 문제점을 파악하는 기술이 도입되었다. 플라스틱 제품의 큰 문제점 중 하나가 치수안정성이다. 특히 박막사출성형품은 게이트의 위치, 냉각채널과 온도에 따라서 변형량이 크게 달라진다. 본 연구에서는 현재 Stackmold방식으로 4개의 Cavity에 4개의 Hot-Runner가 설치된 금형을 통해 생산중인 DVD Tray 박막사출제품의 생산 원가 절감을 위해서 Cavity하나에 한 개의 Hot-Runner를 설계하기 위해서 CAE 해석을 통해 게이트의 위치, 냉각채널과 온도에 따라 비교하여 해석해 최적의 제품 설계를 하였다. CAE 해석에는 상업화된 CAE 프로그램인 Moldflow를 사용하였고, 수지는 PC+ABS를 사용하였다.