• Electrical & Electronic Materials
• /
• v.8 no.1
• /
• pp.56-63
• /
• 1995

MESFETs of the Ti/Au and Ti/Pd/Au gate were fabricated on n-type GaAs. Interdiffusion at Schottky interfaces, Schottky contact properties, and MESFET characteristics with heat treatment were investigated. Ti of Ti/Au contact and Pd of Ti/Pd/Au contact acted as a barrier metal against interdiffusion of Au at >$220^{\circ}C$. Pd of Ti/Pd/Au contact acted as a barrier metal even at >$360^{\circ}C$, however, Ti of Ti/Au contact promoted interdiffusion of Au instead of role of barrier metal. As the heat treatment temperature increases, in the case of both contact, saturated drain current and pinch off voltage decreased, open channel resistance increased, and degree of parameter variation in Ti/Au gate was higher than in Ti/Pd/Au gate at >$360^{\circ}C$ Schottky barrier height of Ti/Au and Ti/Pd/Au contacts was 0.69eV and 0.68eV in the as-deposited state, respectively, and Fermi level was pinned in the vicinity of 1/2Eg. As the heat treatment temperature increases, barrier height of Ti/Pd/Au contact increased, however, decreased at >$360^{\circ}C$ in the case of Ti/Au contact. Ideality factor of Ti/Au contact was nearly constant regardless of heat treatment, however, increased at >$360^{\circ}C$ in the case of Ti/Au contact. From the results above, Ti/Pd/Au was stable gate metal than Ti/Au.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.21 no.5
• /
• pp.46-54
• /
• 1984

A silicon-gate n-well CMOS process with 3 $\mu$m gate length was developed and its possibility for the applications was discussed,. Threshold voltage was easily controlled by ion implantation and 3-$\mu$m gate length with 650 $\AA$ oxide shows ignorable short channel effect. Large value of Al-n+ contact resistance is one of the problems in fabrications of VLSI circuits. Transfer characteristics of CMOS inverter is fairly good and the propagation delay time per stage in ring oscillator with layout of (W/L) PMOS /(W/L) NMOS =(10/5)/(5/5) is about 3.4 nsec. catch-up occurs on substrate current of 3-5 mA in this process and critically dependent on the well doping density and nt-source to n-well space. Therefore, research, more on latch-up characteristics as a function of n-well profile and design rule, especially n+-source to n-well space, is required.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2006.06a
• /
• pp.467-468
• /
• 2006

We report on the fabrication of P3HT-based thin-film transistors (TFT) that consist of indium-zinc-oxide (IZO), PVP (poly-vinyl phenol), and Ni for the source-drain (S/D) electrode, gate dielectric, and gate electrode, respectively. The IZO S/D electrodes of which the work function is well matched to that of P3HT were deposited on a P3HT channel by thermal evaporation of IZO and showed a moderately low but still effective transmittance of ~25% in the visible range along with a good sheet resistance of ${\sim}60{\Omega}/{\square}$. The maximum saturation current of our P3HT-based TFT was about $15{\mu}A$ at a gate bias of -40V showing a high field effect mobility of $0.05cm^2/Vs$ in the dark, and the on/off current ratio of our TFT was about $5{\times}10^5$. It is concluded that jointly adopting IZO for the S/D electrode and PVP for gate dielectric realizes a high-quality P3HT-based TFT.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2005.10a
• /
• pp.111-114
• /
• 2005

Experimental and numerical studies were carried out in order to investigate the processability and the transcriptability of the injection molding of micro structures. For this purpose, we designed a mold insert having micro rib patterns on a relatively thick base part. Mold insert has a base of 2mm thickness, and has nine micro ribs on that base plate. Width and height of the rib are $300{\mu}m\;and\;1200{\mu}m$, respectively. We found a phenomenon similar to 'race tracking', due to 'hesitation' in the micro ribs. As the melt flows, it starts to cool down and melt front located in the ribs near the gate cannot penetrate further because the flow resistance is large in that almost frozen portion. When the base is totally filled, the melt front away from the gate is not frozen yet. Therefore, it flows back to the gate direction through the ribs. Consequently, transcriptability of the rib far from the gate is better. We also verified this phenomenon via numerical simulation. We further investigated the effects of processing conditions, such as flow rate, packing time, packing pressure, wall temperature and melt temperature, on the transcriptability. The most dominant factor that affects the flow pattern and the transcriptability of the micro rib is flow rate. High flow rate and high melt temperature enhance the transcriptability of micro rib structure. High packing time and high packing pressure result in insignificant dimensional variations of the rib. Numerical simulation also confirms that low flow rate causes a short shot of micro ribs and high wall temperature helps the filling of the micro ribs.

• Proceedings of the Korean Institute of Building Construction Conference
• /
• 2023.05a
• /
• pp.147-148
• /
• 2023

Steel doors, which are common in general buildings, do not seal the gap between the door and the floor, so drafts, noise, dust, and lights flow from the outside, and shielding devices are installed in various materials and methods, such as adding magnetic gate paper to the side of the door or installing a gasket under the door, but performance is limited. Accordingly, in order to fundamentally solve these problems, we researched and developed a double gap blocking device that can improve fire resistance and airtightness performance in steel doors. Unlike general products, the double gap blocking device has the advantage of maximizing airtight performance by forming an air layer in the center when the door is closed, as well as greatly improving the fire resistance performance, which is the basic performance of the fire door.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2008.10a
• /
• pp.1293-1296
• /
• 2008

As Flat Panel Display become large in format, the data and gate lines turn into longer, parasitic capacitance and resistance increase, and the display signal is delayed. Three dimensional architecture of multiplexing data registration integrated circuit method is used that divides the data line into several blocks and provides the advantages of high accuracy, rapid selection, and reasonable switching speed.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2008.10a
• /
• pp.1564-1567
• /
• 2008

We demonstrate here a self-aligned printing approach that allows downscaling of printed organic thin-film transistors to channel lengths of 100 - 400 nm. A perfected down-scaled polymer transistors (L= 200 nm) showing high transition frequency over 1.5 Mhz were realized with thin polymer dielectrics, controlling contact resistance, and minimizing overlap capacitance via self-aligned gate configuration.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.181-184
• /
• 1999

This paper presents the accurate deembeding method for pad and parasitics of MOSFET device. rad effects are deembedded using THRU LINE, which is much simpler method without laborious fitting procedure compared with conventional OPEN and SHORT pad modeling. Parasitic resistance extraction uses the algebraic relation between increments of inversion layer charge and oxide capacitance. It is especially adequate for insulating gate junction device. Extracted parasitics are verified through comparing modeled and measured S parameters.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2009.10a
• /
• pp.1197-1199
• /
• 2009

Self-alignment for the fabrication of printed thin film transistors has become of great interest because of the resolution and registration limits of printing technologies. In this work, self-patterning and selfregistration processes are introduced, which do not need surface energy patterning and the resulting minimum gate channel length could be down to $11.2{\mu}m$ with the sheet resistance of 2.6 ${\Omega}/{\square]$ for the source and drain electrodes.

• 한국지구물리탐사학회:학술대회논문집
• /
• 2008.10a
• /
• pp.131-136
• /
• 2008

We performed a non-destructive geophysical survey such as an elastic wave survey, electric specific resistance survey, plate loading test, etc. in order to grasp the structure and status of the ground around the pillar gate and to provide the directions and design data for preservation and maintenance during reconstruction. The result of electric specific resistance survey shows 50-1300 ohm-m range of general electric specific resistance distribution. Besides, the positions around 1m south of stone pillars, between stone pillar No.3 and 4, and 1m north of stone pillar No.2 and 3 show abnormality of relatively lower electric specific resistance than their surroundings. The abnormality of low electric specific resistance appearing between stone pillar No.3 and 4 shows consistency with the abnormal section appearing from the result of elastic wave reflection survey. The result of a plate loading test shows that allowable bearing force is over $10.70tf/m^2$, and the settlement amount at this time was calculated as 19.635mm. The design load during reconstruction of pillar gates was calculated as $16.37t/m^2$ by applying assumption values, which is far more than the allowable bearing force, so it is judged that a measure to strengthen the foundation ground is necessary.