• 제목/요약/키워드: Gate design

검색결과 1,593건 처리시간 0.046초

게이트 라인 물질의 저항률이 TFT-LCD 화소의 동작에 미치는 영향 (Effects of Resistivity of Gate Line Material on TFT-LCD Pixel Operations)

  • 이영삼;최종선
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1998년도 춘계학술대회 논문집
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    • pp.321-324
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    • 1998
  • Pixel-Design Array Simulation Tool(PDAST) was used to profoundly the gate signal distortion and pixel changing capability, which are the most critical limiting factors for high-quality TFT-LCDs. Since PDAST can simulate the gate, data and pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of the resistivity of gate line material on the pixel operations can be effectively analyzed. The gate signal delay, pixel charging ratio, level-shift of the pixel voltage were simulated with varying the resis5tivity of the gate line material. The information obtained from this study could be utilized to design the larger area and finer image quality panel.

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Design of Gate System in Injection Molding of a Dashboard by CAMPmold

  • Choi D. S.;Han K. H.;Kim H. S.;Im Y. T.
    • 한국소성가공학회:학술대회논문집
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    • 한국소성가공학회 2003년도 The Korea-Japan Plastics Processing Joint Seminar
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    • pp.33-39
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    • 2003
  • Injection molding is widely used in producing various plastic parts due to its high productivity and the demand for high precision injection molded products is ever increasing. To achieve successful product quality and precision, the design of gating and runner systems in the injection mold is very important since it directly influences melt flow into the cavity. Some defects such as weld lines and overpacking can be effectively controlled with proper selection of gate locations. In the present study, the design of gate locations in injection molding of a dashboard for automobiles was carried out with CAMPmold, a PC-based simulation system for injection molding. A dummy runner was developed to simulate a runner system in order to increase the efficiency of the analysis. The numbers and locations of gates were varied in the present investigation as that an acceptable design was obtained in terms of reduced maximum pressure and clamping force.

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DACE 모델을 이용한 게이트밸브 단조공정의 최적설계화 (Optimization of Forging Process of Gate Valve using DACE Model)

  • 오승환;공형걸;강정호;박영철
    • 한국기계가공학회지
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    • 제6권1호
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    • pp.71-77
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    • 2007
  • In case of the welding process, a conventional production method of gate valve, it has a merit of light weight, but also a demerit of high production cost and an impossibility in mass production due to work by hand. However, in case of the forging process, it has economic merits and can take a mass production process, too. The main focus of this paper is the optimization of preform in the forging process. This paper proposed an optimal design to improve the mechanical efficiency of gate valve made by forging method instead of welding. the optional design is conducted as application of real response model to Kriging model using computer simulation. Also, from verification of the response model with optimized results we were confirmed that the applications of Kriging method to structural optimum design using finite element analysis and equation are useful and reliable.

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모듈러 설계기법에 기초한 함수구성 (The Function Construction based on Modular Design Technique)

  • 박춘명
    • 한국정보통신학회:학술대회논문집
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    • 한국정보통신학회 2012년도 추계학술대회
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    • pp.918-919
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    • 2012
  • 본 논문에서는 모듈러 설계기법에 기반을 둔 함수분해방법과 입력변수 처리 방법에 관한 설계기법을 제안하였다. 부분 분해방법으로서 행 분할 변수 중 1-열 변수의 입력 값에 따라 함수를 분할하여 컬럼 곱을 구하였다. 또한 제안한 부분 함수는 단일 T-gate를 사용하므로 모듈 라이브러리 방식에서의 제어함수를 생략할 수 있는 장점이 있다. 이를 함수에 적용한 결과 주어진 함수가 비대칭, 불규칙인 경우 기존의 방식에 비래 내부 결선이 약 12%정도, T-gate 수는 16% 정도 감소되어 더욱 간단한 회로설계가 이루어지는 장점이 있음을 보였다.

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80 V급 저전력 반도체 소자의 관한 연구 (Design of 80 V Grade Low-power Semiconductor Device)

  • 심관필;안병섭;강예환;홍영성;강이구
    • 한국전기전자재료학회논문지
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    • 제26권3호
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    • pp.190-193
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    • 2013
  • Power MOSFET and Power IGBT is develop in power savings, high efficiency, small size, high reliability, fast switching, low noise. Power MOSFET can be used high-speed switching transistors devices. Power MOSFET is devices the voltage-driven approach switching devices are design to handle on large power, power supplies, converters. In this paper, design the 80V MOSFET Planar Gate type, and design the Trench Gate type for realization of low on-resistance. For both structures, by comparing and analyzing the results of the simulation and characterization.

배수갑문 테인터 게이트(Tainter Gate)의 진동현상에 관한 모형실험 ( I ) - 문비 밖에서 안으로의 흐름 - (Model Tests Study on Flow-induced Vibration of fainter Gate in Estuary Sulices (I) - Flow from the Gate Outside to the Gate Inside -)

  • 이성행
    • 한국농공학회논문집
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    • 제46권1호
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    • pp.27-34
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    • 2004
  • A model test is carried out to investigate flow-induced vibration of a Tainter gate in estuary sulices. The gate model scaled with the ratio of 1:25 is made of acryl panel dimensioned 0.66m in width, 0.5m in height in the concrete test flume. Firstly, natural frequencies of the model gate are measured and the results are compared with the numerical results in order to verify the model. The amplitudes of the vibration are measured under the different gate opening and water level conditions in flow from the gate outside to the gate inside. Also 5 revised gate models with bottom width increased 0.5 cm each are tested under the different gate opening and water level. The results are analyzed to study the characteristics of the gate vibration. These test results are assessed in comparison with formerly test results, as a result, presents a design method of Tainter gate to reduce the gate vibration and a basic data for the guide manuals of gate management.

16 V 급 NMOSFET 소자의 낮은 게이트 전압 영역에서 출력저항 개선에 대한 연구 (Design and Analysis of 16 V N-TYPE MOSFET Transistor for the Output Resistance Improvement at Low Gate Bias)

  • 김영목;이한신;성만영
    • 한국전기전자재료학회논문지
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    • 제21권2호
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    • pp.104-110
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    • 2008
  • In this paper we proposed a new source-drain structure for N-type MOSFET which can suppress the output resistance reduction of a device in saturation region due to soft break down leakage at high drain voltage when the gate is biased around relatively low voltage. When a device is generally used as a switch at high gate bias the current level is very important for the operation. but in electronic circuit like an amplifier we should mainly consider the output resistance for the stable voltage gain and the operation at low gate bias. Hence with T-SUPREM simulator we designed devices that operate at low gate bias and high gate bias respectively without a extra photo mask layer and ion-implantation steps. As a result the soft break down leakage due to impact ionization is reduced remarkably and the output resistance increases about 3 times in the device that operates at the low gate bias. Also it is expected that electronic circuit designers can easily design a circuit using the offered N-type MOSFET device with the better output resistance.

Local zooming genetic algorithm and its application to radial gate support problems

  • Kwon, Young-Doo;Jin, Seung-Bo;Kim, Jae-Yong;Lee, Il-Hee
    • Structural Engineering and Mechanics
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    • 제17권5호
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    • pp.611-626
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    • 2004
  • On the basis of a structural analysis of radial gate (i.e. Tainter gate), the current paper focuses on weight minimization according to the location of the arms on a radial gate. In spite of its economical significance, there are hardly any previous studies on the optimum design of radial gate. Accordingly, the present study identifies the optimum position of the support point for a radial gate that guarantees the minimum weight satisfying the strength constraint conditions. This study also identifies the optimum position for 2 or 3 radial arms with a convex cylindrical skin plate relative to a given radius of the skin plate curvature, pivot point, water depth, ice pressure, etc. These optimum designs are then compared with previously constructed radial gates. Local genetic and hybrid-type genetic algorithms are used as the optimum tools to reduce the computing time and enhance the accuracy. The results indicate that the weights of the optimized radial gates are appreciably lower than those of previously constructed gates.

사출성형을 위한 게이트.런너 지적설계시스템에 관한 연구 (Intelligent Design System for Gate and Runner in Injection Molding)

  • 이찬우;허용정
    • 한국정밀공학회지
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    • 제18권9호
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    • pp.192-203
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    • 2001
  • The design of gate and runner(delivery system) is one of the most important subject in injection molding. Delivery system is a channel to flow the polymer melt from the injection molding machine to the mold cavities. Also, delivery system affect quality and productivity of the part. The synthesis of delivery system of injection molding has been done empirically, since it requires profound knowledge about the moldability and causal effects on the properties of the part, which are not available to designers through the current CAD systems. GATEWAY is a knowledge module which contains knowledge to permit non-experts as well as mold design experts to generate the acceptable geometries of gate and runner far injection molded parts. A knowledge-based CAD system is constructed by adding the knowledge module, GATEWAY, to an existing geometric modeler. A knowledge-based CAD system is a new tool which enables the concurrent design and CIM with integrated and balanced design decisions at the initial design of injection molding.

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반용융 다이캐스팅 공정의 주조방안 설계 시스템 개발에 관한 연구 (A Study on Development Design System of Gating System for Semi-Solid Diecasting Process)

  • 문찬경;권택환;김영호;최재찬
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 1997년도 추계학술대회 논문집
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    • pp.1028-1031
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    • 1997
  • The SS (Semi-solid) diecasters usually cany out the SS d~ecastmg experiments before producing new products. At the SS diecasting stages, the runner-gate part is always repeatedly corrected, which leads to a lengthened processing time and increased processing cost. The SS diecasting die design should consider component system factors. such as runner, gate, biscuit, overflow and airvent. A large amount of experience is essential in manual assessment and if the design is defective, much time and a great deal of efforts will be wasted in the modification of the d~e. Thus human negligence should be minimized. In this study, die design system for SS diecasting process has been developed to present algonthm of die design, especially runner-gate system. In addition, specific rules and equations for runner-gate system have been presented to avoid too many trials and errors with expensive equipment. It is possible for engineers to be efficient die design of SS diecasting and it will result in reduction of expense and time to be required. And we developed CAD system for SS diecasting die design by AutoLISP language under AutoCAD using proposed algorithm and the database. In addition, we developed the vector analysis program for filling pattern of SS metals.

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