• 제목/요약/키워드: Gate control

검색결과 938건 처리시간 0.025초

Power Loss Modeling of Individual IGBT and Advanced Voltage Balancing Scheme for MMC in VSC-HVDC System

  • Son, Gum Tae;Lee, Soo Hyoung;Park, Jung-Wook
    • Journal of Electrical Engineering and Technology
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    • 제9권5호
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    • pp.1471-1481
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    • 2014
  • This paper presents the new power dissipation model of individual switching device in a high-level modular multilevel converter (MMC), which can be mostly used in voltage sourced converter (VSC) based high-voltage direct current (HVDC) system and flexible AC transmission system (FACTS). Also, the voltage balancing method based on sorting algorithm is newly proposed to advance the MMC functionalities by effectively adjusting switching variations of the sub-module (SM). The proposed power dissipation model does not fully calculate the average power dissipation for numerous switching devices in an arm module. Instead, it estimates the power dissipation of every switching element based on the inherent operational principle of SM in MMC. In other words, the power dissipation is computed in every single switching event by using the polynomial curve fitting model with minimum computational efforts and high accuracy, which are required to manage the large number of SMs. After estimating the value of power dissipation, the thermal condition of every switching element is considered in the case of external disturbance. Then, the arm modeling for high-level MMC and its control scheme is implemented with the electromagnetic transient simulation program. Finally, the case study for applying to the MMC based HVDC system is carried out to select the appropriate insulated-gate bipolar transistor (IGBT) module in a steady-state, as well as to estimate the proper thermal condition of every switching element in a transient state.

관점지향 소프트웨어 개발 방법론과 디자인 패턴을 적용한 출입 보안 시스템 개발 (Development of Secure Entrance System using AOP and Design Pattern)

  • 김태호;천현재;이홍철
    • 한국산학기술학회논문지
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    • 제11권3호
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    • pp.943-950
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    • 2010
  • 출입 보안 시스템은 감시, 로깅, 추적, 인증, 권한부여, 직원 위치 파악, 직원 출입관리, 출입문 관리 등 수많은 기능을 해야 하는 복잡한 시스템이다. 본 논문에서는 관점지향 소프트웨어 개발 방법론(Aspect Oriented Programming: AOP)과 디자인 패턴을 적용해 국내 원자력 발전소의 출입 보안 시스템을 구축하였다. AOP를 이용하면 시스템의 비즈니스 로직과 보안 로직을 완전히 독립적으로 분리해서 시스템 구축이 가능하므로, 출입 보안 시스템의 각 기능별 모듈에 대하여 명확하게 그 역할을 구분해 줄 수 있는 장점이 있다. 이는 잦은 외부환경의 변화에 의한 시스템 변경을 유연하게 대처할 수 있게 하며 AOP의 본래의 장점인 코드 재사용성의 확대, 효율적인 기능 구현 등 이 가능해 진다. 이와 함께 디자인 패턴을 활용하면 일반적인 소프트웨어 개발에서 나타나는 복잡한 문제를 구조화 하여 설계 할 수 있어, 시스템의 안전성 또한 보장 받을 수 있다. 두 방법론의 장점을 활용하여, 그 기능이 복잡한 출입보안 시스템을 안정적으로 설계 구현 할 수 있다.

Static Induction Transistor의 순방향 블로킹 특성 개선에 관한 연구 (A Study on the Improvement of Forward Blocking Characteristics in the Static Induction Transistor)

  • 김제윤;정민철;윤지영;김상식;성만영;강이구
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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    • pp.292-295
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    • 2004
  • The SIT was introduced by Nishizawa. in 1972. When compared with high-voltage, power bipolar junction transistors, SITs have several advantages as power switching devices. They have a higher input impedance than do bipolar transistors and a negative temperature coefficient for the drain current that prevents thermal runaway, thus allowing the coupling of many devices in parallel to increase the current handling capability. Furthermore, the SIT is majority carrier device with a higher inherent switching speed because of the absence of minority carrier recombination, which limits the speed of bipolar transistors. This also eliminates the stringent lifetime control requirements that are essential during the fabrication of high-speed bipolar transistors. This results in a much larger safe operating area(SOA) in comparison to bipolar transistors. In this paper, vertical SIT structures are proposed to improve their electrical characteristics including the blocking voltage. Besides, the two dimensional numerical simulations were carried out using ISE-TCAD to verify the validity of the device and examine the electrical characteristics. A trench gate region oxide power SIT device is proposed to improve forward blocking characteristics. The proposed devices have superior electrical characteristics when compared to conventional device. Consequently, the fabrication of trench oxide power SIT with superior stability and electrical characteristics is simplified.

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Improvement in the bias stability of zinc oxide thin-film transistors using an $O_2$ plasma-treated silicon nitride insulator

  • 김웅선;문연건;권태석;박종완
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2009년도 제38회 동계학술대회 초록집
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    • pp.180-180
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    • 2010
  • Thin film transistors (TFTs) based on oxide semiconductors have emerged as a promising technology, particularly for active-matrix TFT-based backplanes. Currently, an amorphous oxide semiconductor, such as InGaZnO, has been adopted as the channel layer due to its higher electron mobility. However, accurate and repeatable control of this complex material in mass production is not easy. Therefore, simpler polycrystalline materials, such as ZnO and $SnO_2$, remain possible candidates as the channel layer. Inparticular, ZnO-based TFTs have attracted considerable attention, because of their superior properties that include wide bandgap (3.37eV), transparency, and high field effect mobility when compared with conventional amorphous silicon and polycrystalline silicon TFTs. There are some technical challenges to overcome to achieve manufacturability of ZnO-based TFTs. One of the problems, the stability of ZnO-based TFTs, is as yet unsolved since ZnO-based TFTs usually contain defects in the ZnO channel layer and deep level defects in the channel/dielectric interface that cause problems in device operation. The quality of the interface between the channel and dielectric plays a crucial role in transistor performance, and several insulators have been reported that reduce the number of defects in the channel and the interfacial charge trap defects. Additionally, ZnO TFTs using a high quality interface fabricated by a two step atomic layer deposition (ALD) process showed improvement in device performance In this study, we report the fabrication of high performance ZnO TFTs with a $Si_3N_4$ gate insulator treated using plasma. The interface treatment using electron cyclotron resonance (ECR) $O_2$ plasma improves the interface quality by lowering the interface trap density. This process can be easily adapted for industrial applications because the device structure and fabrication process in this paper are compatible with those of a-Si TFTs.

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양해법과 음해법을 이용한 영산강에서의 부정류해석 (Unsteady Flow Analysis in the Youngsan River Using Explicit and Implicit Finite Difference Methods)

  • 최성욱;여운광;주철;김창완;오유창
    • 물과 미래
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    • 제24권4호
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    • pp.49-58
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    • 1991
  • 영산강 유역의 89년 7월 호우에 대하여 두가지 유한차분법을 이요한 부정류해석을 실시하였다. 유한 차분법으로는 양해법의 경우 Leap Frog 기법을, 음해법은 Preissmann 기법을 사용하였고 지배방정식은 쌍곡선형 편미분방정식의 일종인 Saint Venant 식을 이용하였다. 외부경계조건으로는 상류단의 유량과 하류단의 조위를 이요하였으며 하구언을 내부경계조건으로 포함시켰다. 지천에서의 유입량과 상류단에서의 유량은 저류함수법에 의한 결과로써 시간별 입력자료로 사용되었다. 비교적 상류에 해당되는 나주지점에서 실측자료, 저류함수법 그리고 두 수치모형에 의한 계산값을 비교해본 결과 해의 정확도는 만족스러웠고 실측자료가 없는 중하류지점에서도 두 모형에 의한 계산값을 비교함으로써 상대적으로 신뢰할 수 있음을 알았다. 본 연구를 통하여 기존의 수문학적 홍수추적방법과 더불어 수치해석에 의한 부정류모형이 홍수예경보업무에 충분히 이용될 수 있음을 알 수 있었으며, 앞으로 본모형을 이용한 홍수시 배수갑문의 최적운영방안등의 연구도 기대된다 하겠다.

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족삼리(足三里) 자침(刺鐵)이 생체(生體)(생체)에 미치는 영향(影響)에 대한 실험연구동향 (PubMed 검색을 통한 문헌고찰) (The Trend of Experimental Study on the Effect of Acupuncture at $ST_{36}$(Zusanli))

  • 김윤희;임윤경;이현
    • Korean Journal of Acupuncture
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    • 제22권1호
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    • pp.133-150
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    • 2005
  • Objective : The purpose of this study is to examine the tendency of experimental studies on the physiological effects of acupuncture at $ST_{36}$(Zusanli). Methods : We investigated 69 theses (10 Korean and 59 international) which were searched by the keyword 'Zusanli' through PubMed website, and that were experimented with manual acupuncture or electroacupuncture on healthy human subjects or normal animals. Results : The 69 theses were classified into iou groups based on the main topic which is related with the influence of acupuncture stimulation at $ST_{36}$(Zusanli), such as digestive system, nervous system, immune system, and cardiovascular system. The main results found in this study are : 1. Acupuncture at $ST_{36}$(Zusanli) increases gastric mobility. And such effect is related with vagal nerve and opioid pathway. 2. Acupuncture at $ST_{36}$(Zusanli) is valuably related with cerebral cortex. And it influences on the cerebrum activities. 3. Acupuncture at $ST_{36}$(Zusanli) has noticeable analgesic effect, which is related with Opioid mechanism, Gate control and SP 4. Acupuncture at $ST_{36}$(Zusanli) increases immunity Conclusion . Acupuncture at $ST_{36}$(Zusanli) has many effects on digestive system, nervous system, immune system, and cardiovascular system.

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16 비트 EISC 마이크로 프로세서에 관한 연구 (A Study on 16 bit EISC Microprocessor)

  • 조경연
    • 한국멀티미디어학회논문지
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    • 제3권2호
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    • pp.192-200
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    • 2000
  • 8비트와 16비트 마이크로 프로세서는 소규모 제어기기에 많이 사용되고 있다. 이러한 실장 제어용 마이크로 프로세서는 CP와 메모리 및 입출력 회로가 하나의 반도체에 집적되어야 하므로 회로가 간단하고, 코드 밀도가 높은 것이 요구되고 있다. 본 논문에서는 코드 밀도가 높은 EISC(Extendable Instruction Set Computer)구조를 가지는 16비트 마이크로 프로세서인 SE1608을 제안한다. SE1608은 8개의 범용 레지스터를 가지며, 16비트 고정 길이 명령어, 짧은 오프셋 인덱스 어드레싱과 짧은 상수 오퍼랜드 명령어를 가지며, 확장 레지스터와 확장 프래그를 사용하여 오프셋 및 상수 오퍼랜드를 확장할 수 있다. SE1608은 FPGA로 구현하여 약 12,000 게이트가 소요되었으며, 8MHz에서 모든 기능이 정상적으로 동작하는 것을 확인하였고, 크로스 어셈블러와 크로스C /C++컴파일러 및 명령어 시뮬레이터를 설계하고 동작을 검증하였다. SE1608의 코드 밀도는 16비트 마이크로 프로세서인 H-8300의 140%, NM10200의 115%로 현격하게 높은 장점을 가진다. 따라서 하드웨어가 간단하고, 프로그램 메모리 크기가 작아지므로 실장 제어용 마이크로 프로세서에 적합하여 폭 넓은 활용이 기대된다.

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Dynamic Pattern 기법을 이용한 주문형 반도체 결함 검출에 관한 연구 (A Study on the Fault Detection of ASIC using Dynamic Pattern Method)

  • 심우제;정해성;강창훈;지민석;안동만;홍교영;홍승범
    • 한국항행학회논문지
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    • 제17권5호
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    • pp.560-567
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    • 2013
  • 본 논문에서는 일반적으로 사용되고 있는 개발 및 분석용 프로그램을 이용하여 시험요구서가 개발되지 않은 ASIC을 대상으로 결함을 검출하는 방법을 제안한다. 시험요구서가 없는 경우, 회로의 동작을 파악하기 힘들어 어떤 칩에서 결함이 발생하였는지 발견하기 어렵다. 따라서 ASIC의 로직 데이터를 분석하여 결함 검출을 위한 시험요구서를 작성하고, 시험요구서에 따라 제작된 Dynamic Pattern 신호를 이용하여 게이트 레벨에서 입출력 핀 신호 제어를 통해 고장진단을 한다. 실험결과 제안된 기법을 비메모리 회로에 적용하여 우수한 결함 검출능력을 확인하였다.

Real-Time HIL Simulation of the Discontinuous Conduction Mode in Voltage Source PWM Power Converters

  • Futo, Andras;Kokenyesi, Tamas;Varjasi, Istvan;Suto, Zoltan;Vajk, Istvan;Balogh, Attila;Balazs, Gergely Gyorgy
    • Journal of Power Electronics
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    • 제17권6호
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    • pp.1535-1544
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    • 2017
  • Advances in FPGA technology have enabled fast real-time simulation of power converters, filters and loads. FPGA based HIL (Hardware-In-the-Loop) simulators have revolutionized control hardware and software development for power electronics. Common time step sizes in the order of 100ns are sufficient for simulating switching frequency current and voltage ripples. In order to keep the time step as small as possible, ideal switching function models are often used to simulate the phase legs. This often produces inferior results when simulating the discontinuous conduction mode (DCM) and disabled operational states. Therefore, the corresponding measurement and protection units cannot be tested properly. This paper describes a new solution for this problem utilizing a discrete-time PI controller. The PI controller simulates the proper DC and low frequency AC components of the phase leg voltage during disabled operation. It also retains the advantage of fast real-time execution of switch-based models when an accurate simulation of high frequency junction capacitor oscillations is not necessary.

흑색 황산3가크롬을 이용한 태양열 흡열판 선택흡수막 도금기술 (Technology of selective absorber coatings on solar collectors using black chromium+3 sulfate acid on substrates)

  • 엄태인;여운택;김동찬
    • 한국태양에너지학회 논문집
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    • 제33권3호
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    • pp.27-35
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    • 2013
  • One of the most important factors that have a large influence on performance of the solar water heater system is performance of the solar collector, more detailedly, coating technology on the surface of the solar collector, which can provide high solar absorptance and low emittance. The core of the coating technology is to coat solar selective surfaces. In this study, various performance experiments are carried out using $Cr_2(SO_4)_3{\cdot}15H_2O$ coating technology. Here, IGBT(Insulated Gate Bipolar Transistor) of 5000A-15V was used as the surface processing rectifier which can stably output power and also can control voltage and current. The plating solution mainly contains black chrome$^{+3}$ concentration, H-y Conductivity, N-u Complex, NF Additive and NC-2 Wetter. Before applying the black chrome coating on the copper plate, optimal conditions are provided by using various preprocessing methods such as removal of fat, activation, electrolytic polishing, nickel strike, copper sulfate plating and bright neckel plating, and then the automatic continuous coating experiment are performed according to plating time and cathode current density. In the experiment, after the removal of fat, chemical polishing, nickel strike and activation processes as the preprocessing methods, the black chrome coating was performed in a plate solution temperature of $28^{\circ}C$ and a cathode current density of $18A/cm^2$ for 90 seconds. The thickness of chrome and nickel on the coated plate is $0.389{\mu}m$, $159{\mu}m$ respectively. As a result of the coating experiment, it showed the most excellent performance having a high solar absorptance of 98% and a low emittance of $5{\pm}1%$ when the black chrome surface had a thickness of $0.398{\mu}m$.