• Proceedings of the KIEE Conference
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• 1999.07f
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• pp.2783-2785
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• 1999

A fast switching gate driver suitable for high performance self resonant electronic ballasts is presented. The proposed gate driver has negligible switching loss and driving loss owing to pnpn structure and zero voltage switching( ZVS ); moreover, the gate driver has frequency control capability. Therefore, a self resonant inverter using proposed gate driver can operate as external exciting resonant inverters. The experiments confirm that the proposed gate driver perform the desired operations over full power control range for 40W fluorescent lamp electronic ballast.

• 전기의세계
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• v.17 no.2
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• pp.6-10
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• 1968

The conversive limitation of electric energy for the thyristor inverter is analysed under the boundary conditions which the term of a negative inverse voltage is longer than that of the turn off time of the thyristor under commutation. It is clear that the maximum electric energy conversion is affected by the turn off time of the thyristor, the reactance of a commutation reactor, the capacity of a commutation condenser and the voltage of Direct current source. It is useful for design the thyrister invertor and the motor speed control to apply the above conclusion.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.287.2-287.2
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• 2016

Silicon has considerably good characteristics on electron, hole mobility and its price. With 2-D sinlge-layer Graphene/n-Si heterojunction solar cell shows that in one sun condition exhibit power conversion efficiency(PCE) of 10.1%. This photovoltaic effect was achieved by applying gate voltage to the Schottky junction of the heterostructure solar cell. Energy band diagram shows that Schottky barrier between Si and graphene can be adjust by the external electric field. because of the fermi level of the graphene can be changed by external gate voltage, we can control the Schottkky barrier of the heterostructure solar cell. The ratio between generated power of solar cell and consumption electrical power is remarkable. Since we use the graphene as the top gate electrode, most of the sun light can penetrate into the active area.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.2
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• pp.76-80
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• 2014

Dual-gate PCRAM which unify capacitor-less DRAM and NVM using a PCM instead of a typical SONOS flash memory is proposed as 1 transistor. $VO_2$ changes its phase between insulator and metal states by temperature and field. The front-gate and back-gate control NVM and DRAM, respectively. The feasibility of URAM is investigated through simulation using c-interpreter and finite element analysis. Threshold voltage of NVM is 0.5 V that is based on measured results from previous fabricated 1TPCM with $VO_2$. Current sensing margin of DRAM is 3 ${\mu}A$. PCM does not interfere with DRAM in the memory characteristics unlike SONOS NVM. This novel unified dual-gate PCRAM reported in this work has 1 transistor, a low RESET/SET voltage, a fast write/erase time and a small cell so that it could be suitable for future production of URAM.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1885-1890
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• 2003

In this paper, we have developed the voltage controlled crystal oscillator (VCXO) with positive emitter coupled logic(PECL). The VCXO is a crystal oscillator which includes a varactor diode and associated circuitry allowing the frequency to be changed by application of a voltage across that diode. The characteristics of the PECL has the delay time less than 2 ns and the faster logic gate, and the high level output greater than 2.3 V and the low level output smaller than 1.68 V.

• Journal of Power Electronics
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• v.17 no.4
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• pp.1117-1126
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• 2017

The main contribution of this paper is the use of sensorless active diodes to generate the gate signals for a three-phase boost-rectifier with a self-powered control scheme. The sensorless operation is achieved making use of the gate control signals generated by the active diode schemes on each of the switching devices using a pulse width half-controlled boost rectifier modulation technique (PWM-HCBR). The proposed scheme synchronizes the gate control signals with a three phase voltage supply. Autonomous operation is obtained making use of the output DC bus to feed the control circuitry, the active diodes and the driver circuitry. The three-phase boost-rectifier is supplied by a three-phase permanent magnet electric generator powered by a solar concentrator dish with variable voltage and variable frequency conditions. Experimental results report an efficiency of up to 94.6% for 25 W and an input of 3.6 V peak per phase with 450.

• Journal of IKEEE
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• v.25 no.2
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• pp.381-387
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• 2021

As Head-Mounted Displays(HMDs), which are mainly used to maximize realism in games and videos, have experienced increased demand and expanded scope of use in education and training, there is growing interest in methods to enhance the performance of conventional HMDs. In this study, a methodology to utilize Carbon NanoTubes(CNTs) to improve the performance of gate drivers that send control signals to each pixel circuit of the HMD is discussed. This paper proposes a new circuit design method that replaces the transistors constituting the buffer part of the conventional gate driver with transistors incorporating CNTs and compare the performance of the suggested gate drive with that of a gate driver comprising only conventional transistors via simulations. According to the simulation results, by including CNTs in the gate driver, the output voltage can be increased by approximately 0.3V compared to the conventional gate driver high voltage(1.1V) at a speed of 12.5 GHz and the gate width also can be reduced by up to 20 times.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.9
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• pp.56-63
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• 1997

There generally exists a large variation in the thereshold voltages of the flash EEPROM cells after they are erased by using th fowler-nordheim tunneling, thereby getting some cells to be overeased. If the overerased cells are programmed with the conventional one-step programming scheme where an 12-13V pulse with the duration of 100.mu.S is applie don the control gate for the programming, they can suffer from the significant degradation of the reliability of the gate oxide. A two-step programming schem, where an 8/12 V pulse with a duration of 50.mu.S for each voltage is applied on the control gate for the programming, has been studied to solve the problem. The experimental results hav eshown that there is little difference in the programming characteristics between those two schemes, whereas the degradation of the gate oxide due to the programming can be significantly reduced with the two-step programming scheme compared to that with the one-step programming scheme. This is possibly because the positive charge stored in the floating gate of the overerased cells is compensate dwith the electrons injected into the floating gate while the 8V pulse is applied on the control gate, which leaves the overerased cells in the normally erased state after the duration of the 8V pulse.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.3
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• pp.47-52
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• 2017

This research scrutinizes the data retention characteristics of the MLC NAND Flash Memory instigated by the loss effect of trapped charge when the memory is in the state of program saturation. It is attributed to the threshold voltage saturation phenomenon which engenders an interruption to the linear increase of the voltage in the memory cell. This phenomenon is occasioned by the outflow of the trapped charge from the floating gate to the control gate, which has been programmed by the ISPP (Incremental Step Pulse Programming), via Inter-Poly Dielectric (IPD). This study stipulates the significant degradation of thermal retention characteristics of threshold voltage in the saturation region in contrast to the ones in the linear region. Thus the current study evaluates the data retention characteristics of voltage after the program with a repeated reading test in various measurement conditions. The loss effect of trapped charge is found in the IPD layer located between the floating gate and the control gate especially in the nitride layer of the IPD. After the thermal stress, the trapped charge is de-trapped and displays the impediment of the characteristic of reliability. To increase the threshold saturation voltage in the NAND Flash Memory, the storage ability of the charge in the floating gate must be enhanced with a well-thought-out designing of the module in the IPD layer.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.176-183
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• 2017

There is a problem of long erase and program times in testing large-density memories. Also, there is a need of testing the VT voltages of EEPROM cells at each step during the reliability test. In this paper, a cell verification module is designed for a 512kb EEPROM and a CG (control gate) driver is proposed for measuring the VT voltages of a split gate EEPROM having negative erase VT voltages. In the proposed cell verification module, asymmetric isolated HV (high-voltage) NMOS devices are used to apply negative voltages of -3V to 0V in measuring erase VT voltages. Since erasing and programming can be done in units of even pages, odd pages, or a chip in the test time reduction mode, test time can be reduced to 2ms in testing the chip from 4ms in testing the even and the odd pages.