• Journal of Power Electronics
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• v.11 no.2
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• pp.218-227
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• 2011

The subject of variable step size maximum power point tracking (MPPT) algorithms has been addressed in the literature. However, most of the addressed algorithms tune the variable step size according to two variables: the photovoltaic (PV) array voltage ($V_{PV}$) and the PV array current ($I_{PV}$). Therefore, both the PV array current and voltage have to be measured. Recently, maximum power point trackers that arc based on a single variable ($I_{PV}$ or $V_{PV}$) have received a great deal of attention due to their simplicity and ease of implementation, when compared to other tracking techniques. In this paper, two methods have been proposed to design a variable step size MPPT algorithm using only a single current sensor for stand-alone battery storage PV systems. These methods utilize only the relationship between the PV array measured current and the converter duty cycle (D) to automatically adapt the step change in the duty cycle to reach the maximum power point (MPP) of the PV array. Detailed analyses and flowcharts of the proposed methods are included. Moreover, a comparison has been made between the proposed methods to investigate their performance in the transient and steady states. Finally, experimental results with field programmable gate arrays (FPGAs) are presented to verify the performance of the proposed methods.

• Macromolecular Research
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• v.17 no.7
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• pp.528-532
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• 2009

The size and shape of free volume (FV) holes available in membrane materials control the rate of gas diffusion and its permeability. Based on this principle, a segmented, thermo-sensitive polyurethane (TSPU) membrane with functional gate, i.e., the ability to sense and respond to external thermo-stimuli, was synthesized. This smart membrane exhibited close-open characteristics to the size of the FV hole and water vapor permeation and thus can be used as smart food packaging materials. Differential scanning calorimetry (DSC), dynamic mechanical analysis (DMA), positron annihilation lifetimes (PAL) and water vapor permeability (WVP) were used to evaluate how the morphological structure of TSPU and the temperature influence the FV holes size. In DSC and DMA studies, TSPU with a crystalline transition reversible phase showed an obvious phase-separated structure and a phase transition temperature at $53^{\circ}C$ (defined as the switch temperature and used as a functional gate). Moreover, the switch temperature ($T_s$) and the thermal-sensitivity of TSPU remained available after two or three thermal cyclic processes. The PAL study indicated that the FV hole size of TSPU is closely related to the $T_s$. When the temperature varied cyclically from $T_s-10{\circ}C$ to $T_s+10^{\circ}C$, the average radius (R) of the FV holes of the TSPU membrane also shifted cyclically from 0.23 to 0.467 nm, exhibiting an "open-close" feature. As a result, the WVP of the TSPU membrane also shifted cyclically from 4.30 to $8.58\;kg/m^2{\cdot}d$, which produced an "increase-decrease" response to the thermo-stimuli. This phase transition accompanying significant changes in the FV hole size and WVP can be used to develop "smart materials" with functional gates and controllable water vapor permeation, which support the possible applications of TSPU for food packaging.

• Journal of Sensor Science and Technology
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• v.14 no.3
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• pp.137-143
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• 2005

Research in the field of biosensor has enormously increased over the recent years. The metal-oxide semiconductor field effect transistor (MOSFET) type protein sensor offers a lot of potential advantages such as small size and weight, the possibility of automatic packaging at wafer level, on-chip integration of biosensor arrays, and the label-free molecular detection. We fabricated MOSFET protein sensor and proposed the gold-black electrode as the gate metal to improve the response. The experimental results showed that the output voltage of MOSFET protein sensor was varied by concentration of albumin proteins and the gold-black gate increased the response up to maximum 13 % because it has the larger surface area than that of planar-gold gate. It means that the expanded gate allows a larger number of ligands on same area, and makes the more albumin proteins adsorbed on gate receptor.

• Transactions on Electrical and Electronic Materials
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• v.10 no.6
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• pp.193-195
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• 2009

This paper aims to develop a low gate source voltage ($V_{gs}$) N-LDMOS element that is fully operational at a CMOS Logic Gate voltage (3.3 or 5 V) realized using the 0.35 μm BCDMOS process. The basic structure of the N-LDMOS element presented here has a Low $V_{gs}$ LDMOS structure to which the thickness of a logic gate oxide is applied. Additional modification has been carried out in order to obtain features of an improved breakdown voltage and a specific on resistance ($R_{sp}$). A N-LDMOS element can be developed with improved features of breakdown voltage and specific on resistance, which is an important criterion for power elements by means of using a proper structure and appropriate process modification. In this paper, the structure has been made to withstand the excessive electrical field on the drain side by applying the double gate oxide structure to the channel area, to improve the specific on resistance in addition to providing a sufficient breakdown voltage margin. It is shown that the resulting modified N-LDMOS structure with the feature of the specific on resistance is improved by 31%, and so it is expected that optimized power efficiencies and the size-effectiveness can be obtained.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.83-83
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• 2009

We studied about the effect of newly developed etchant for spacer etch process in gate patterning. With the 110nm CMOS technology, first, we changed the gate pattern size and investigated the variation of spacer etch profile according to the difference in gate length. Second, thickness of spacer nitride was changed and effect of etch ant on difference in nitride thickness was observed. In addition to these, spacer etch power was added as test item for variation of etch profile. We investigated the etch profiles with SEM and TEM analysis was used for plasma damage check. With these results we could check the process margins for gate patterning which could hold best performance and choose the condition for best spacer etch profile.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.137-140
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• 1998

An active-matrix LCD using thin film transistors (TFT) has been widely recognized as having potential for high-quality color flat-panel displays. Pixel-Design Array Simulation Tool (PDAST) was used to profoundly understand the gate si후미 distortion and pixel charging capability. which are the most critical limiting factors for high-quality TFT-LCDs. Since PDAST can simulate the gate, data and pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of the resistivity of gate line material on the pixel operations can be effectively analyzed. The gate signal delay, pixel charging ratio and level-shift of the pixel voltage were simulated with varying the parameters. The information obtained from this study could be utilized to design the larger area and finer image quality panel.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.368-368
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• 2010

Using TFTs crystallized by MICC and ELA, electron mobility and threshold voltage were measured according to various substrate temperature from $-40^{\circ}C$ to $100^{\circ}C$. Basic curve, $V_G-I_D$, is also measured under various stress time from 1s to 10000s. Consequently, due to the passivation effect and number of grains, mobility of MICC is varied in the range of -8% ~ 7.6%, while that of ELA is varied from -11.04% ~ 13.25%. Also, since $V_G-I_D$ curve is dominantly affected by grain size, active layer interface, the graph remained steady under the various gate bias stress time from 1s to 10000s. This proves the point that MICC can be alternative technic to ELA.

• 제어로봇시스템학회:학술대회논문집
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• 1988.10a
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• pp.414-417
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• 1988

Recently PLC pursues faster scanning time, circuit confidence, reliability improvement, and smaller size. To obtain above all merit, custom IC(Gate Array) is developed. Custom IC includes 5 main blocks and 2 auxiliary blocks. The 5 main blocks process faster sequential instruction execution by only logic gate using hexa instruction code system. And the 2 auxiliary blocks generate baud rate clock (153.6 KHz, 76.8KHz) to communicate between PLC and computer or programmers.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.1
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• pp.185-192
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• 1995

In this study, very fine photoresist pattern was examined using the image reversal process. And very fine photoriesist pattern (less than 0.2um) was obtsined by optimizing the exposure and reversal baking condition of photoresist. The produced pattern does not show the loss of thickness, and has a sparp negative edge profile. also, the ion implanted 0.25um T-shaped gate MESFET was fabricated using this resist pattern and the directional evaporation of gate metal. The fabricated MESFET has the maximum transconductance of 302 mS/mm, and the threshold voltage of -1.8V, and the drain saturation current of this MESFET was 191 mA/mm.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1606-1608
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• 2002

The triac is a bidirectional triode with blocking and conducting characteristics used in motor control or heater power control. This greatly simplifies the circuits required for the control of the full wave AC Power by reducing the number of power handling components and by reducing the size and complexity of the gate control circuit.[3] In this paper, We can understand measurement results of analysis which have been made on the electrical characteristics of triac with gate diffusion time for the gate area.