• Design & Manufacturing
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• v.14 no.1
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• pp.1-7
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• 2020

In this study, the variation of the shrinkage in the thickness direction of the molded parts according to the gate size of the polymer core fabricated through the 3D printer using the SLS method was studied. The polymer cores are laser sintered and the powder material is nylon base PA2200. The polymer cores have lower heat transfer rate and rigidity than the metal core due to the characteristics of the material. Therefore, the injection molding test conditions are set to minimize the deformation of the core during the injection process. The resin used in the injection molding test is a PP material. The packing condition was set to 80, 90 and 100% of the maximum injection pressure for each gate size. The runner diameter used was ∅3mm, and the gates were fabricated in semicircle shapes with cross sections 1, 2, and 3 ㎟, respectively. Thickness measurement was performed for 10 points at 2.5 mm intervals from the point 2.5 mm away from the gate, and the shrinkage to thickness was measured for each point. The shrinkage rate according to the gate size tends to decrease as the cross-sectional area decreases as the maximum injection pressure increases. The average thickness shrinkage rate was close to 0% when the packing pressure was 90% for the gate area of 1mm2. When the holding pressure was set to 100%, the shrinkage was found to decrease by 3% from the standard dimension due to the over-packing phenomenon. Therefore, the smaller the gate, the more closely the molded dimensions can be molded due to the high pressure generation. It was confirmed that precise packing process control is necessary because over-packing phenomenon may occur.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.12
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• pp.768-772
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• 1999

A new TFT-LCD panel with air-bridge type gate to data line inter-crossing has been proposed and its characteristics have been measured. The proposed structure has air-gap between gate and data line inter-crossing. This air-bridge TFT-LCD panel has very small capacitance between gate and data line. The new panes structure achieves 9 times fast signal propagation compared with conventional panel, which enables to have enough design margin for 20-inch diagonal and larger size UXGA panel. We have examined thermal and mechanical durability of new panel to verify applicability for commercial AMLCD production. After TEOS and polyimide passivation, this panel withstood a thermal stress at $250^{\circ}C$ and a mechanical stress during the rubbing process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.389-389
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• 2010

In this paper, an investigation of the benefits of gate oxide for 8" the manufacturing of Trench MOSFETs and its impact on device performance is presented. Layout dimensions of trench power MOSFETs have been continuously reduced in order to decrease the specific on-resistance, maintaining equal vertical dimensions. We discuss experimental results for devices with a pitch size down fabricated with an unconventional gate trench topology and a simplified manufacturing scheme. The fabricated Trench MOSFETs are observed the trench gate oxidation by SEM.

• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.208-211
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• 1997

We have fabricated a single-electron-tunneling(SET) transistor with a dual gate geometry based on the SOI structure prepared by SIMOX wafers. The split-gate is the lower-gate is the lower-level gate and located ∼ 100${\AA}$ right above the inversion layer 2DEG active channel, which yields strong carrier confinement with fully controllable tunneling potential barrier. The transistor is operating at low temperatures and exhibits the single electron tunneling behavior through nano-size quantum dot. The Coulomb-Blockade oscillation is demonstrated at 15mK and its periodicity of 16.4mV in the upper-gate voltage corresponds to the formation of quantum dots with a capacity of 9.7aF. For non-linear transport regime, Coulomb-staircases are clearly observed up to four current steps in the range of 100mV drain-source bias. The I-V characteristics near the zero-bias displays typical Coulomb-gap due to one-electron charging effect.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.6
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• pp.433-439
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• 2011

Poly Si TFTs (poly silicon thin film transistors) with p channel those are annealed HT (high temperature) with gate poly crystalline silicon and LT (low temperature) with metal gate electrode were fabricated on quartz substrate using the analyzed data and compared according to the activated grade silicon thin films and the size of device channel. The electrical characteristics of HT poly-Si TFTs increased those are the on current, electron mobility and decrease threshold voltage by the quality of particles of active thin films annealed at high temperature. But the on/off current ratio reduced by increase of the off current depend on the hot carrier applied to high gate voltage. Even though the size of the particles annealed at low temperature are bigger than HT poly-Si TFTs due to defect in the activated grade poly crystal silicon and the grain boundary, the characteristics of LT poly-Si TFTs were investigated deterioration phenomena those are decrease the electric off current, electron mobility and increase threshold voltage. The results of transconductance show that slope depend on the quality of particles and the amplitude depend on the size of the active silicon particles.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.05a
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• pp.529-530
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• 2010

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.4
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• pp.652-657
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• 1987

This paper describes an application of CMOS Gate Array Integrated Cricuits to the implementation of three functional units: A Multiplexer, Time Switch, and Demultiplexer in the Switching Network and Digital Line Concentrator of TDX-1 system, which is a fully digital time division electronic switching system in Korea. The application of CMOS Gate Array Integrated Circuits significantly improves the overall system performance in terms of power consumption, cost, size, reliability, and timing margin, etc.

• Journal of the Korea Institute of Military Science and Technology
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• v.10 no.4
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• pp.145-151
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• 2007

This paper considers new filter gains for the ${\alpha}\;-\;{\beta}$ tracker which is optimized particularly to minimize the tracking gate size. Optimizing the performance index which is composed of tracking errors due to target maneuver and measurement noise is not different from the existing method to obtain the ${\alpha}\;-\;{\beta}$ gains. However, holding the probability 0.997 that a target exists in the tracking gate and minimizing the gate size produce the new result not similar to the existing ${\alpha}\;-\;{\beta}$ gains.

• Proceedings of the KSR Conference
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• 2007.11a
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• pp.1438-1444
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• 2007

Standard Gate Turn Off (GTO) Thyristor drive technology results in inhomogeneous turn-on and turn-off transients which in turn needs costly dv/dt and di/dt snubber circuits. Added to this GTO is bulky in size, needs external cooling, slower switching time etc. The development of high voltage Insulated Gate Bipolar Transistor (IGBT) have given new device advantage in the areas where they compete with conventional GTO technology. Indian Railway has developed first IGBT based traction converter and was commissioned in November 2006. Some of the supremacy of IGBT are smaller in size, no external cooling is required, built in power supply which enhances reliability, lower switching losses which leads to higher efficiency, reduced gate drive, high frequency operation in real time etc. These advantages are highlighted along with IGBT Traction system in operation.

• Transactions of Materials Processing
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• v.15 no.5 s.86
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• pp.347-353
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• 2006

The delivery system such as sprue, runner and gate is a waste of resin in injection molding operation. In this study the reduction of runner size has been investigated using injection molding CAE softwares, Moldflow and Moldex3D, and commercial CFD Softwares, Fluent and Polyflow. To verify the computational results experiment was performed. There were three considerations in deciding optimal runner size in this study: minimum pressure at the gate that makes resin fully filled in the cavity, minimum runner size that compensates shrinkage of resin in the cavity, and frozen layer thickness formed in the runner during injection. Through the computer simulations the optimal runner size that satisfies those three considerations has been decided. Although the computational results among the softwares were slightly different, it was enough to predict the optimal runner size. The previous runner diameter was 8 mm and predicted optimal size was 5 mm. This was verified by injection molding experiment. Thus, the way of CAE application in deciding optimal runner size adapted in this study would be appropriated.