• Title/Summary/Keyword: Gate Security

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Development Hi-DPI Algorithm for High Speed Packet Filtering of Anti-DDoS based on HW (하드웨어 기반 Anti-DDoS 대응 장비 고속 패킷 필터링을 위한 Hi-DPI 알고리즘 연구)

  • Kim, Jeom Goo
    • Convergence Security Journal
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    • v.17 no.2
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    • pp.41-51
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    • 2017
  • The explosive increase in the range of Internet usage gradually makes the speed and capacity of network high-speed, rapidly evolving it into mass storage. Accordingly, network equipment such as switch and router are coping with it through hardware-based rapid technological evolution, but as the technological development of the most basic and essential network security system in the hyper-connected society requires frequent alterations and updates about the security issues and signatures of tens of thousands, so it is not easy to overcome the technical limitations based on the software. In this paper, to improve problems in installing and operating such anti-DDoS devices, we propose a Hi-DPI algorithm best reflecting the hardware characteristics and parallel processing characteristics of FPGA (Field Programmable Gate Array), and would verify the practicality.

Design and Implementation of PDA-based Image Surveillance System for Harbor Security using IP Camera

  • Shim, Joon-Hwan
    • Journal of Navigation and Port Research
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    • v.31 no.9
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    • pp.779-784
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    • 2007
  • This paper describes a new progressive embedded Internet Protocol(IP) camera available for real-time image transmission. It was applied for ship safety and security on seashore area. The functions of developed embedded system was more effective and excellent than conventional systems. Nowadays, each nation has established harbor security systems to jump up their ports to international port. Recently Incheon port has tried to change man security into center security system used by image security system. The security system of Incheon port has some advantages like effectivity of security system and reduction of manpower and cost, installed by image security system with CCTV cameras at the entrance gate and around the fence. Thus in this paper, we have designed and implemented a Personal Digital Assistants(PDA) based Image Surveillance System for Harbor Security using IP Camera under ubiquitous environment. This system has big advantages which are more effective in an emergency and low cost and small manpower than conventional systems.

Trends in Toffoli gate decomposition (Toffoli gate 분해에 대한 동향)

  • Hyun-Jun Kim;Se-Jin Lim;Hwa-Jeong Seo
    • Proceedings of the Korea Information Processing Society Conference
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    • 2023.05a
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    • pp.165-167
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    • 2023
  • 양자 컴퓨터는 기존의 클래식 컴퓨터와 달리 양자역학 원리를 활용해 정보 처리를 수행하며, 특정 문제들을 훨씬 빠르게 해결할 수 있다. 양자 컴퓨터는 큐빗을 기본 단위로 사용하고, 아다마르 게이트, CNOT 게이트, 파울리 게이트, 토플리 게이트 등을 조합하여 양자 회로를 구성한다. Toffoli 게이트는 유니버설 게이트 중 하나로, 세 개의 큐빗을 입력받아 조건부 (Controlled-Controlled) NOT 연산을 수행한다. 이 게이트는 복잡한 작업을 기본 양자 게이트로 분해할 수 있어, 회로의 게이트 수, 깊이 및 오류율 측면에서 최적화할 수 있다. 기본 양자 게이트 중 T 게이트는 노이즈와 오류에 영향을 받을 수 있으므로, T 게이트의 수와 깊이를 최적화하는 것이 중요하다. 본 논문은 Toffoli 게이트 분해를 통해 양자 회로의 게이트 수와 깊이를 최적화하는 방법을 조사한다.

Privacy-Preserving Cloud Data Security: Integrating the Novel Opacus Encryption and Blockchain Key Management

  • S. Poorani;R. Anitha
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.17 no.11
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    • pp.3182-3203
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    • 2023
  • With the growing adoption of cloud-based technologies, maintaining the privacy and security of cloud data has become a pressing issue. Privacy-preserving encryption schemes are a promising approach for achieving cloud data security, but they require careful design and implementation to be effective. The integrated approach to cloud data security that we suggest in this work uses CogniGate: the orchestrated permissions protocol, index trees, blockchain key management, and unique Opacus encryption. Opacus encryption is a novel homomorphic encryption scheme that enables computation on encrypted data, making it a powerful tool for cloud data security. CogniGate Protocol enables more flexibility and control over access to cloud data by allowing for fine-grained limitations on access depending on user parameters. Index trees provide an efficient data structure for storing and retrieving encrypted data, while blockchain key management ensures the secure and decentralized storage of encryption keys. Performance evaluation focuses on key aspects, including computation cost for the data owner, computation cost for data sharers, the average time cost of index construction, query consumption for data providers, and time cost in key generation. The results highlight that the integrated approach safeguards cloud data while preserving privacy, maintaining usability, and demonstrating high performance. In addition, we explore the role of differential privacy in our integrated approach, showing how it can be used to further enhance privacy protection without compromising performance. We also discuss the key management challenges associated with our approach and propose a novel blockchain-based key management system that leverages smart contracts and consensus mechanisms to ensure the secure and decentralized storage of encryption keys.

Intelligent Monitoring System for Solitary Senior Citizens with Vision-Based Security Architecture (영상보안 구조 기반의 지능형 독거노인 모니터링 시스템)

  • Kim, Soohee;Jeong, Youngwoo;Jeong, Yue Ri;Lee, Seung Eun
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2022.05a
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    • pp.639-641
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    • 2022
  • With the increasing of aging population, a lot of researches on monitoring systems for solitary senior citizens are under study. In general, a monitoring system provides a monitoring service by computing the information of vision, sensors, and measurement values on a server. Design considering data security is essential because a risk of data leakage exists in the structure of the system employing the server. In this paper, we propose a intelligent monitoring system for solitary senior citizens with vision-based security architecture. The proposed system protects privacy by ensuring high security through an architecture that blocks communication between a camera module and a server by employing an edge AI module. The edge AI module was designed with Verilog HDL and verified by implementing on a Field Programmable Gate Array (FPGA). We tested our proposed system on 5,144 frame data and demonstrated that a dangerous detection signal is generated correctly when human motion is not detected for a certain period.

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Implementation and characterization of flash-based hardware security primitives for cryptographic key generation

  • Mi-Kyung Oh;Sangjae Lee;Yousung Kang;Dooho Choi
    • ETRI Journal
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    • v.45 no.2
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    • pp.346-357
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    • 2023
  • Hardware security primitives, also known as physical unclonable functions (PUFs), perform innovative roles to extract the randomness unique to specific hardware. This paper proposes a novel hardware security primitive using a commercial off-the-shelf flash memory chip that is an intrinsic part of most commercial Internet of Things (IoT) devices. First, we define a hardware security source model to describe a hardware-based fixed random bit generator for use in security applications, such as cryptographic key generation. Then, we propose a hardware security primitive with flash memory by exploiting the variability of tunneling electrons in the floating gate. In accordance with the requirements for robustness against the environment, timing variations, and random errors, we developed an adaptive extraction algorithm for the flash PUF. Experimental results show that the proposed flash PUF successfully generates a fixed random response, where the uniqueness is 49.1%, steadiness is 3.8%, uniformity is 50.2%, and min-entropy per bit is 0.87. Thus, our approach can be applied to security applications with reliability and satisfy high-entropy requirements, such as cryptographic key generation for IoT devices.

FPGA Implementation of Rijndael Algorithm (Rijndael 블록암호 알고리즘의 FPGA 구현)

  • 구본석;이상한
    • Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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    • 2001.11a
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    • pp.403-406
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    • 2001
  • 본 논문에서는 차세대 표준 알고리즘(AES: Advanced Encryption Standard)인 Rijndael 알고리즘의 고속화를 FPGA로 구현하였다. Rijndael 알고리즘은 미국 상무부 기술 표준국(NIST)에 의해 2000년 10월에 차세대 표준으로 선정된 블록 암호 알고리즘이다. FPGA(Field Programmable Gate Array)는 아키텍쳐의 유연성이 가장 큰 장점이며, 근래에는 성능면에서도 ASIC에 비견될 정도로 향상되었다. 본 논문에서는 128비트 키 길이와 블록 길이를 가지는 암호화(Encryption)블럭을 Xilinx VirtexE XCV812E-8-BG560 FPGA에 구현하였으며 약 15Gbits/sec의 성능(throughput)을 가진다. 이는 현재까지 발표된 FPGA Rijndael 알고리즘의 구현 사례 중 가장 빠른 방법 중의 하나이다.

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Discussions on the Conservation of Urban Heritage Based on the 1960s' Projects for Changing the Deoksugung Palace Wall and the Daehanmun Gate (1960년대 덕수궁 담장과 대한문의 변경 계획에 따른 도시 유산 보존 논의)

  • Kee, Sehwang;Park, So-Hyun
    • Journal of the Architectural Institute of Korea Planning & Design
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    • v.35 no.10
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    • pp.53-62
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    • 2019
  • The purpose of this study is to analyze the way historical heritage was dealt with during the massive urban development period of the 1960s through the case of Deoksugung Palace. The wall of Deoksugung Palace was rebuilt and relocated in 1961. Later, it was rebuilt and relocated again in 1968, and Daehanmun Gate was soon moved back too. I analyzed the opinions of the Seoul Metropolitan Government, the Cultural Heritage Committee, experts and citizens that occurred during this process and reached the following conclusion. First, in 1961, the existing stone walls of Deoksugung Palace were rebuilt rather than restored and conserved for the urbanscape at the time. Second, in the 1960s, the Cultural Heritage Committee focused on the conservation of the origin of Daehanmun Gate, while citizens valued the overall harmony and function of Deoksugung Palace. Third, unlike the 1970s project led by the president to renovate national security and national defense sites, there was a call from citizens to realize the preservation of Deoksugung Palace.

A Design of an AES-based Security Chip for IoT Applications using Verilog HDL (IoT 애플리케이션을 위한 AES 기반 보안 칩 설계)

  • Park, Hyeon-Keun;Lee, Kwangjae
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.67 no.1
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    • pp.9-14
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    • 2018
  • In this paper, we introduce an AES-based security chip for the embedded system of Internet of Things(IoT). We used Verilog HDL to implement the AES algorithm in FPGA. The designed AES module creates 128-bit cipher by encrypting 128-bit plain text and vice versa. RTL simulations are performed to verify the AES function and the theory is compared to the results. An FPGA emulation was also performed with 40 types of test sequences using two Altera DE0-Nano-SoC boards. To evaluate the performance of security algorithms, we compared them with AES implemented by software. The processing cycle per data unit of hardware implementation is 3.9 to 7.7 times faster than software implementation. However, there is a possibility that the processing speed grow slower due to the feature of the hardware design. This can be solved by using a pipelined scheme that divides the propagation delay time or by using an ASIC design method. In addition to the AES algorithm designed in this paper, various algorithms such as IPSec can be implemented in hardware. If hardware IP design is set in advance, future IoT applications will be able to improve security strength without time difficulties.

Design of Extendable QCA 4-to-2 Encoder Based on Majority Gate (확장성을 고려한 다수결 게이트 기반의 QCA 4-to-2 인코더 설계)

  • Kim, Tae-Hwan;Jeon, Jun-Cheol
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.26 no.3
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    • pp.603-608
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    • 2016
  • Encoding means converting or processing form or format of information into the other forms to standardize, secure, improve processing speed, store saving spaces and etc. Also, Encoding is converting the information so as to do transmit other form on the sender's information to the receiver in Information-Communication. The device that is conducting the processing is called the encoder. In this dissertation, proposes an encoder of the most basic 4-to-2 encoder. proposed encoder consists of two OR-gate and the proposed structure designs and optimize the spacing of the cell for the purpose of minimizing noise between wiring. Through QCADesigner conducts simulation of the proposed encoder and analyzes the results confirm the effectiveness.