• 전기전자학회논문지
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• 제24권1호
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• pp.364-367
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• 2020

본 논문에서는 OR논리게이트를 적용한 순차전압제어방식의 독립형 PV-ESS 시스템을 나타내고 있다. 저압연계방식으로 용량확대에 따른 문제점들을 가지고 있었던 기존 독립형 PV-ESS 시스템에 고압의 아날로그 방식의 순차전압제어 방식을 적용함으로써 고효율, 저가격이 가능한 독립형 PV-ESS 시스템을 제안한다. 본 논문은 기존 24V 태양광 단위 모듈의 직렬연결 확장형 고압 배터리의 출력전압 384V을 3상 DC to AC 인버터의 입력 전압으로 하여 인버터의 출력 전압과 출력 전력을 AC380V@60Hz와 10kW로 구성하였다. PSIM 시뮬레이션에 의한 이론 해석의 타당성을 입증하기 위해 실험을 통해 OR 논리 게이트를 적용한 순차전압제어시스템의 동작 특성을 확인하였다.

• Nuclear Engineering and Technology
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• 제50권6호
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• pp.860-868
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• 2018

This article presents a new design of earthquake instrumentation that is suitable for quick decision-making after the seismic event at the nuclear power plant (NPP). The main objective of this work is to ensure more availability of the NPP by expediting walk-down period when the seismic wave is incident. In general, the decision-making to restart the NPP after the seismic event requires more than 1 month if an earthquake exceeds operating basis earthquake level. It affects to the plant availability significantly. Unnecessary shutdown can be skipped through quick assessments of operating basis earthquake, safe shutdown earthquake events, and damage status to structure, system, and components. Multidecision parameters such as cumulative absolute velocity, peak ground acceleration, Modified Mercalli Intensity Scale, floor response spectrum, and cumulative fatigue are discussed. The implementation scope on the field-programmable gate array platform of this work is limited to cumulative absolute velocity, peak ground acceleration, and Modified Mercalli Intensity. It can ensure better availability of the plant through integrated decision-making process by automatic assessment of NPP structure, system, and components.

• ETRI Journal
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• 제38권4호
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• pp.645-653
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• 2016

This paper demonstrates the performance of a metal-substrate power module with multiple fabricated chips for a high current electrical application, and evaluates the proposed module using a 1.5-kW sinusoidal brushless direct current (BLDC) motor. Specifically, the power module has a hybrid structure employing a single-layer heat-sink extensible metal board (Al board). A fabricated motor driver IC and trench gate DMOSFET (TDMOSFET) are implemented on the Al board, and the proper heat-sink size was designed under the operating conditions. The fabricated motor driver IC mainly operates as a speed controller under various load conditions, and as a multi-phase gate driver using an N-ch silicon MOSFET high-side drive scheme. A fabricated power TDMOSFET is also included in the fabricated power module for three-phase inverter operation. Using this proposed module, a BLDC motor is operated and evaluated under various pulse load tests, and our module is compared with a commercial MOSFET module in terms of the system efficiency and input current.

• 전자공학회논문지C
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• 제36C권6호
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• pp.37-43
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• 1999

고성능 VLSI 설계를 위한 pipeline 형태의 Reed-Solomon을 구현하였다. Shortened RS code의 경우에 있어서 기존의 parallel recursive cell 방식이나[1] 다중 클락 설계와 같은 접근과는 달리 작은 면적에서 단일 클락으로 동작할 수 있는 이중 수소(two-way addressing) 방식의 Euclid 계산을 제안하였다. 이러한 방식은 recursive cell을 병렬 처리하는 Euclid 계산 방식에 비해 면적이나 소비 전력에 있어 장점을 갖고 있음을 synthesis와 전력 모의실험을 통해 검증하였다. 본 설계는 면적상으로 parallerl recursive cell을 이용한 단일 클락euclid 회로가 약 5,000 gate임에 비하여 40% 정도 감소한 3,000 gate 정도에 구현할 수 있었다. 또한 전력 소비면으로는 기존의 recursive cell을 이용한 다중 클락 euclid 회로가 6mW 이상의 전력을 소비하는 반면에 본 설계는 3mW대의 전력 소비를 보여 현격한 차이를 보였다.

• 대한전기학회논문지
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• 제35권12호
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• pp.541-554
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• 1986

This paper presents the results of driving performance analysis of permanent magnet synchronous motor using a microprocessor based control system. The system consists of three phase power transistor inverters, three phase controlled rectifier, three central processing units, and sensors. The three CPUs are, respectively, used to generate PWM control signals for the inverter generating three phase sine wave, to generate the gate control signals for firing the converter, and to supervise other two CPUs. The supervisor is used to compute PI control algtorithm to three phase reference sine wave for the inverter. It is also used to maintain a constant voltage frequency ratio for the converter operating as a constant torque controller. The inverter CPU retrieves precomputed PWM patterns from look up tables because of computation speed limitations found in almost available microprocessors. The converter CPU also retrieves precomputed gate control patterns from another look-up tables. For protecting the control ststem from any damage by extraordinary over currents, the supervisor receives the data from current sensor, CT, and break down the CB to isolate the circuits from source. A resolver has a good performance characteristics of overall speed range, especially on low speed range. Therefor the speed control accuracy is impoved. The microprocessor based PM synchronous motor control system, thus, has many advantages such as constant torque characteristics, improvement of wave, limitation on extraordinary over currents, improvement of speed control accuracy, and fast response speed control using multi-CPU and look-up tables.

• 시스템엔지니어링학술지
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• 제17권2호
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• pp.49-60
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• 2021

The Core Protection Calculator System (CPCS) is vital for plant safety as it ensures the required Specified Acceptance Fuel Design Limit (SAFDL) are not exceeded. The CPCS generates trip signals when Departure from Nucleate Boiling Ratio (DNBR) and Local Power Density (LPD) exceeds their predetermined setpoints. These setpoints are established based on the operating margin from the analysis that produces the SAFDL values. The goal of this research is to create a simplified CPCS that optimizes operating margin for I-SMRs. Because the I-SMR is compact in design, instrumentation placement is a challenge, as it is with Ex-core detectors and RCP instrumentation. The proposed CPCS addresses the issue of power flux measurement with In-Core Instrumentation (ICI), while flow measurement is handled with differential pressure transmitters between Steam Generators (SG). Simplification of CPCS is based on a Look-Up-Table (LUT) for determining the CEA groups' position. However, simplification brings approximations that result in a loss of operational margin, which necessitates compensation. Appropriate compensation is performed based on the result of analysis. FPGAs (Field Programmable Gate Arrays) are presented as a way to compensate for the inadequacies of current systems by providing faster execution speeds and a lower Common Cause Failure rate (CCF).

• Journal of information and communication convergence engineering
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• 제6권2호
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• pp.177-181
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• 2008

The more improved the Internet and the information technology, the stronger cryptographic system is required which can satisfy the information security on the platform of personal hand-held devices or smart card system. This paper introduces a case study of designing an elliptic curve cryptographic processor of a high performance that can be suitably used in a wireless communicating device or in an embedded system. To design an efficient cryptographic system, we first analyzed the operation hierarchy of the elliptic curve cryptographic system and then implemented the system by adopting a serial cell multiplier and modified Euclid divider. Simulation result shows that the system was correctly designed and it can compute thousands of operations per a second. The operating frequency used in simulation is about 66MHz and gate counts are approximately 229,284.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 B
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• pp.653-656
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• 2003

We have designed embedded web sewer system and ported Linux operating system version 2.4.5 at our system. And then We implemented to control and monitor widely separated hardware and implemented to monitor widely separated image using CMOS image sensor HV7131B. Web server is the Boa web server with General Public License. We designed for this system using of Intel's SA1110 ARM core base processor and connecting input and output device at GPIO port of SA1110. Device driver of General purpose I/O for Embedded Linux OS is designed. And then the application program controlling driver is implemented to use of common gate interface C language. User is available to control and monitor at client PC. This method have benefit to reduce the Expenditure of hardware design and development time against PC base system and have various and capacious application against firmware base system.

• 한국조명전기설비학회지:조명전기설비
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• 제7권3호
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• pp.57-66
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• 1993

본 연구에서는 순차식 게이트구동방식을 사용하여 L, C 공진회로로 링크된 2조의 full-bridge 인버터회로를 병렬제어하는 기법을 제안하고 있다.MOSFET로 구성된 각 인버터는 한 개의 등가스위치 모델로 되어 직렬공진형 등가 half-bridge 인버터회로를 구성하고 있다. 게이트 제어기법으로 각 소자의 구동 주기를 분할 제어함으로서 소자의 직병렬 운전이 가능한 순차식 게이트 구동방식을 사용하고 이에 따른 인버터의 회로동작 모드를 분석하고 해석하였다.시뮬레이션을 통한 회로 해석 결과 각 인버터단과 소자의 전압 및 전류분담이 적절히 이루어지고 있음을 알 수 있었고 안정된 회로동작이 이루어지고 있음을 확인하였다.

• Journal of Electrical Engineering and Technology
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• 제10권4호
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.