• 한국진공학회지
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• 제7권3호
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• pp.195-200
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• 1998

본 연구에서는 강유전체 박막의 게이트 산화물로 사용한 $Pt/SrBi_2Ta_2O_9(SBT)/CeO_2/Si(MFS)$와 Pt/SBT/Si(MFS) 구조의 결정 구조 및 전기적 성질 의 차이를 연구하였다. XRD 및 SEM 측정 결과 SBT/$CeO_2$/Si박막은 약5nm정도의 $SiO_2$층 이 형성되었고 비교적 평탄한 계면의 미세구조를 가지는 반면, SBT/Si는 각각 약6nm와 7nm정도의 $SiO_2$층과 비정질 중간상층이 형성되었음을 알 수 있다. 즉 CeO2 박막을 완충층 으로 사용함으로써 SBT박막과 Si기판의 상호 반응을 적절히 억제할 수 있음을 확인하였다. Pt/SBT/$CeO_2/Pt/SiO_2$/와 Pt/SBT/Pt/$SiO_2$/Si구조에서 Polarization-Electric field(P-E) 특 성을 비교해 본 결과 CeO2박막의 첨가에 따라 잔류분극값은 감소하였고 항전계값은 증가하 였다. MFIS구조에서 memory window값은 항전계값과 직접적 관련이 있으므로 이러한 항 전계값의 증가는 MFIS구조에서의 memory window값이 증가할 수 있음을 나타낸다. Pt-SBT(140nm)/$CeO_2$(25nm)/Si구조에서 Capacitance-Voltage(C-V) 측정 결과로부터 동작 전압 4-6V에서 memory wondows가 1-2V정도로 나타났다. SBT박막의 두께가 증가할수록 memory window값은 증가하였는데 memory wondows가 1-2V정도로 나타났다. SBT박막의 두께가 증가할수록 memory window값은 증가하였는데 이는 SBT박막에 걸리는 전압강하가 증가하기 때문인 것으로 생각되어진다. Pt/SBT/$CeO_2$/Si의 누설전류는 10-8A/cm2정도였고 Pt/SBT/Si 구조에서는 약10-6A/cm2정도로 약간 높은 값을 나타내었다.

• 한국표면공학회지
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• 제29권6호
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• pp.809-815
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• 1996

$Y_2O_3$-based metal-insulator-semiconductor (MIS) structure on p-Si(100) has been studied. Films were prepared by UHV reactive ionized cluster beam deposition (r-ICBD) system. The base pressure of the system was about $1 \times 10^{-9}$ -9/ Torr and the process pressure $2 \times 10^{-5}$ Torr in oxygen ambience. Glancing X-ray diffraction(GXRD) and in-situ reflection high energy electron diffracton(RHEED) analyses were performed to investigate the crystallinity of the films. The results show phase change from amorphous state to crystalline one with increasingqr acceleration voltage and substrate temperature. It is also found that the phase transformation from $Y_2O_3$(111)//Si(100) to $Y_2O_3$(110)//Si(100) in growing directions takes place between $500^{\circ}C$ and $700^{\circ}C$. Especially as acceleration voltage is increased, preferentially oriented crystallinity was increased. Finally under the condition of above substrate temperature $700^{\circ}C$ and acceleration voltage 5kV, the $Y_2O_3$films are found to be grown epitaxially in direction of $Y_2O_3$(1l0)//Si(100) by observation of transmission electron microscope(TEM). Capacitance-voltage and current-voltage measurements were conducted to characterize Al/$Y_2O_3$/Si MIS structure with varying acceleration voltage and substrate temperature. Deposited $Y_2O_3$ films of thickness of nearly 300$\AA$ show that the breakdown field increases to 7~8MV /cm at the same conditon of epitaxial growing. These results also coincide with XPS spectra which indicate better stoichiometric characteristic in the condition of better crystalline one. After oxidation the breakdown field increases to 13MV /cm because the MIS structure contains interface silicon oxide of about 30$\AA$. In this case the dielectric constant of only $Y_2O_3$ layer is found to be $\in$15.6. These results have demonstrated the potential of using yttrium oxide for future VLSI/ULSI gate insulator applications.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 추계학술대회 논문집 전기물성,응용부문
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• pp.77-78
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• 2006

최근 flexible OLED의 구동에 사용하기 위한 유기박막트랜지스터(Organic Thin Film Transistor, OTFT)의 연구에서는 용매에 용해되어 spin coating이 가능한 재료의 개발에 관심을 두고 있다. 현재 pentacene으로는 아직 spin coating으로 제작할 수 있는 상용화된 제품이 없고 spin coating이 가능한 활성층 물질(active material)로 P3HT가 쓰이고 있다. 본 연구에서는 용해 가능한 P3HT 활성층 물질과 여러 종류의 용해 가능한 게이트 절연물(gate insulator, Gl)을 사용하여 안정된 소자를 구현할 수 있는 공정을 개발하는 목적으로 metal-insulator-semironductor(MIS) 소자를 제작하여 C-V 특성을 측정하고 분석하였다. 먼저 7mm${\times}$7mm 크기의 pyrex glass 시편 위에 바닥 전극으로 $1600{\AA}$ Au을 증착하고 spin coating 방식을 이용하여 PVP, PVA, PVK, BCB, Pl의 5종류의 게이트 절연층을 각각 형성하였고 그 위에 같은 방법으로 P3HT를 코팅하였다. P3HT 코팅 시 bake 공정의 유무와 spin rpm의 변화에 따른 P3HT의 두께를 측정하였다. Gl의 종류별로 주파수에 따른 capatltancc를 측정하여 비교, 분석하였다. C-V 측정 결과 PVP, PVA, PVK, BCB, Pl의 단위 면적당 capacitance 값은 각각 1.06, 2.73, 2.94, 3.43, $2.78nF/cm^2$로 측정되었다. Threshold voltage, $V_{th}$는 각각 -0.4, -0.7, -1.6, -0.1, -0.2V를 나타냈다. 주파수에 따른 capacitance 변화율을 측정한 결과 Gl 물질 모두 주파수가 높을수록 capacitance가 점점 감소하는 경향을 보였으나 1${\sim}$2nF 이내의 범위에서 작은 변화율만 나타냈다. P3HT의 두께와 bake 온도를 변화시켜 C-V 값을 측정한 결과 차이는 없었다. FE-SEM으로 관찰한 결과에서도 두께나 온도에 따른 P3HT의 표면 morphology 차이를 확인할 수 없었다. 본 연구에서 PVK와 P3HT의 조합이 수율(yield)면에서 가장 안정적이면서 $3.43\;nF/cm^2$의 가장 높은 capacitance 값을 나타내고 $V_{th}$ 값 또한 -1.6V로 가장 낮은 값을 보였다.

• 공업화학
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• 제24권3호
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• pp.219-226
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• 2013

차세대 전자 디스플레이 관련 제품의 휴대편리성, 유연성, 경량화, 대형화 등의 요구조건을 확보할 수 있는 유기반도체 소재기반 소프트 일렉트로닉스에 많은 관심이 모아지고 있다. 소프트 일렉트로닉스의 응용분야로는 전자 신문, 전자 책, 스마트카드, RFID 태그, 태양전지, 휴대용 컴퓨터, 센서, 메모리 등이 있으며, 핵심소자는 유기 전계효과 트랜지스터(organic field-effect transistor, OFET)이다. OFET의 고성능화를 위해서는 유기반도체, 절연체, 전극 구성소재들이 최적화 구조를 형성하도록 적층되어야 한다. 필름형성화 과정에서 대부분의 유기반도체 소재는 결합력이 약한 van der Waals 결합으로 자기조립 결정구조를 형성하므로, 이들의 결정성 필름구조는 주위 환경(공정변수 및 기질특성)에 의해 크게 달라진다. 특히 기질의 표면 에너지(surface energy) 및 표면 거칠기(surface roughness)에 따라 유기반도체 박막 내 결정 구조 및 배향 등은 크게 달라져, OFET의 전기적 특성에 큰 차이를 미친다. 유기친화적 절연층 소재 및 표면개질화는 전하이동에 유리하도록 용액 및 증착공정 유기반도체 박막의 결정구조 및 배향을 유도시켜 OFET의 전기적 성능을 향상시킬 수 있다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.170-170
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• 2010

Thin-film transistors (TFT) have become the key components of electronic and optoelectronic devices. Most conventional thin-film field-effect transistors in display applications use an amorphous or polycrystal Si:H layer as the channel. This silicon layers are opaque in the visible range and severely restrict the amount of light detected by the observer due to its bandgap energy smaller than the visible light. Therefore, Si:H TFT devices reduce the efficiency of light transmittance and brightness. One method to increase the efficiency is to use the transparent oxides for the channel, electrode, and gate insulator. The development of transparent oxides for the components of thin-film field-effect transistors and the room-temperature fabrication with low voltage operations of the devices can offer the flexibility in designing the devices and contribute to the progress of next generation display technologies based on transparent displays and flexible displays. In this thesis, I report on the dc performance of transparent thin-film transistors using amorphous indium tin zinc oxides for an active layer. $SiO_2$ was employed as the gate dielectric oxide. The amorphous indium tin zinc oxides were deposited by RF magnetron sputtering. The carrier concentration of amorphous indium tin zinc oxides was controlled by oxygen pressure in the sputtering ambient. Devices are realized that display a threshold voltage of 4.17V and an on/off ration of ${\sim}10^9$ operated as an n-type enhancement mode with saturation mobility with $15.8\;cm^2/Vs$. In conclusion, the fabrication and characterization of thin-film transistors using amorphous indium tin zinc oxides for an active layer were reported. The devices were fabricated at room temperature by RF magnetron sputtering. The operation of the devices was an n-type enhancement mode with good saturation characteristics.

• ETRI Journal
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• 제26권6호
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• pp.575-582
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• 2004

Fully-depleted silicon-on-insulator (FD-SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the single- raised (SR) and double-raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self-heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self-heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a $1.1\;{\mu}m^2$ 6T-SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra-thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices.

• 대한전자공학회논문지SD
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• 제42권12호
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• pp.13-18
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• 2005

본 논문에서는 Poly-ethylene-terephthalate (PET) 기판 위에 Organic Thin Film Transistor (OTFT)와 Organic Light Emitting Diode (OLED)를 직렬 연결시킨 픽셀과 64 x 64 픽셀로 구성된 어레이를 제작하여 동작을 시연하였다. OTFT는 PET 기판과의 호환성을 고려하여 Poly 4-vinylphenol을 게이트 절연체로, 펜타센을 활성층으로 사용하여 제작되었다. 개별 소자 수준에서는 이동도가 $1.0\;cm^2/V{\cdot}sec$로 나타났으나, 어레이에서는 $0.1\~0.2\;cm^2/V{\cdot}sec$로 약 10배 정도 감소하였다. 어레이의 동작을 분석하였고 OTFT의 OLED에 대한 전류구동능력을 확인하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.324-326
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• 2016

In this study, we have investigated indium tin zinc oxide (ITZO) as an active channel for non-volatile memory (NVM) devices. The electrical and memory characteristics of NVM devices using multi-stack gate insulator SiO2/SiOx/SiOxNy (OOxOy) with Si-rich SiOx for charge storage layer were also reported. The transmittance of ITZO films reached over 85%. Besides, ITZO-based NVM devices showed good electrical properties such as high field effect mobility of 25.8 cm2/V.s, low threshold voltage of 0.75 V, low subthreshold slope of 0.23 V/dec and high on-off current ratio of $1.25{\times}107$. The transmission Fourier Transform Infrared spectroscopy of SiOx charge storage layer with the richest silicon content showed an assignment at peaks around 2000-2300 cm-1. It indicates that many silicon phases and defect sources exist in the matrix of the SiOx films. In addition, the characteristics of NVM device showed a retention exceeding 97% of threshold voltage shift after 104 s and greater than 94% after 10 years with low operating voltage of +11 V at only 1 ms programming duration time. Therefore, the NVM fabricated by high transparent ITZO active layer and OOxOy memory stack has been applied for the flexible memory system.

• 한국재료학회지
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• 제21권2호
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• pp.115-119
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• 2011

Si Nanowire (NW) field effect transistors (FETs) were fabricated on hard Si and flexible polyimide (PI) substrates, and their electrical characteristics were compared. Si NWs used as channels were synthesized by electroless etching method at low temperature, and these NWs were refined using a centrifugation method to get the NWs to have an optimal diameter and length for FETs. The gate insulator was poly(4-vinylphenol) (PVP), prepared using a spin-coating method on the PI substrate. Gold was used as electrodes whose gap was 8 ${\mu}m$. These gold electrodes were deposited using a thermal evaporator. Current-voltage (I-V) characteristics of the device were measured using a semiconductor analyzer, HP-4145B. The electrical properties of the device were characterized through hole mobility, $I_{on}/I_{off}$ ratio and threshold voltage. The results showed that the electrical properties of the TFTs on PVP were similar to those of TFTs on $SiO_2$. The bending durability of SiNWs TFTs on PI substrate was also studied with increasing bending times. The results showed that the electrical properties were maintained until the sample was folded about 500 times. But, after more than 1000 bending tests, drain current showed a rapid decrease due to the defects caused by the roughness of the surface of the Si NWs and mismatches of the Si NWs with electrodes.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권4호
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• pp.265-275
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• 2010

In this work, reliable methodology for device design is presented. Based on this method, the underlap length has been optimized for minimizing the gateinduced drain leakage (GIDL) in a 22-nm node 4-terminal (4-T) silicon-on-insulator (SOI) fin-shaped field effect transistor (FinFET) by TCAD simulation. In order to examine the effects of underlap length on GIDL more realistically, doping profile of the source and drain (S/D) junctions, carrier lifetimes, and the parameters for a band-to-band tunneling (BTBT) model have been experimentally extracted from the devices of 90-nm channel length as well as pnjunction test element groups (TEGs). It was confirmed that the underlap length should be near 15 nm to suppress GIDL effectively for reliable low standby power (LSTP) operation.