• Proceedings of the KAIS Fall Conference
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• 2007.11a
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• pp.133-135
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• 2007

PMMA (polymethyl metha crylate) 유기막의 농도별 최적화를 위하여 1, 2, 4, 6, 8 wt.%의 PMMA 농도별로 Al/PMMA/ITO/Glass 구조의 MIM (metal- insulator-metal) 캐패시터 소자를 제작하였다. 유기 절연층의 형성은 ITO/Glass 기판 위에 PMMA를 용질로, Anisle을 용매로 사용하여 스핀코팅법으로 소자를 형성하였다. 제작된 소자에 대해 농도에 따른 전기적 특성을 조사한 결과 누설전류는 2wt.% 농도의 PMMA로 제작된 소자에서 0.3 pA로 가장 우수한 결과를 얻을 수 있었다. 또한 동일한 PMMA 농도로 제작된 캐패시터 소자의 정전용량은 1.2 nF으로 가장 좋은 결과를 얻을 수 있었으며, 계산된 값과 매우 유사한 값을 얻을 수 있었다.

• Journal of IKEEE
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• v.23 no.3
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• pp.811-816
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• 2019

The silicon-adsorbed oxygen(Si-O) superlattice grown by ultra high vacuum-chemical vapor deposition(UHV-CVD) was introduced as an epitaxial barrier for silicon quantum electron devices. The current-voltage (I-V) measurement results show the stable and good insulating behavior with high breakdown voltage. It is apparent that the Si-O superlattice can serve as an epitaxially grown insulating layer as possible replacement of silicon-on-insulator(SOI). This thick barrier may be useful as an epitaxial insulating gate for field effect transistors(FETs). The rationale is that it should be possible to fabricate a FET on top of another FET, moving one step closer to the ultimate goal of future silicon-based three-dimensional integrated circuit(3DIC).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.1-8
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• 2008

We fabricated flexible electrophoretic display(EPD) driven by organic thin film transistors(OTFTs) on plastic substrate. We designed the W/L of OTFT to be 15, considering EPD's transient characteristics. The OTFTs employed bottom contact structure and used Al for gate electrode, the cross-linked polyvinylphenol for gate insulator, pentacene for active layer. The plastic substrate was coated by PVP barrier layer in order to remove the islands which were formed after pre-shrinkage process and caused the electrical short between bottom scan and top data metal lines. Pentacene active layer was confined within the gate electrodes so that the off current was controlled and reduced by gate electrodes. Especially, PVA/Acryl double layers were inserted between EPD panel and OTFT-backplane in order to protect OTFT-backplane from the damages created by lamination process of EPD panel on the backplane and also accommodate pixel electrodes through via holes. From the OTFT-backplane the mobility was $0.21cm^2/V.s$, Ion/Ioff current ratio $10^5$. The OTFT-EPD panel worked successfully and demonstrated to display some patterns.

• ETRI Journal
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• v.38 no.4
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• pp.675-684
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• 2016

This paper demonstrates the effect of fluoride-based plasma treatment on the performance of $Al_2O_3/AlGaN/GaN$ metal-insulator-semiconductor heterostructure field effect transistors (MISHFETs) with a T-shaped gate length of $0.20{\mu}m$. For the fabrication of the MISHFET, an $Al_2O_3$ layer as a gate dielectric was deposited using atomic layer deposition, which greatly decreases the gate leakage current, followed by the deposition of the silicon nitride layer. The silicon nitride layer on the gate foot region was then selectively removed through a reactive ion etching technique using $CF_4$ plasma. The etching process was continued for a longer period of time even after the complete removal of the silicon nitride layer to expose the $Al_2O_3$ gate dielectric layer to the plasma environment. The thickness of the $Al_2O_3$ gate dielectric layer was slowly reduced during the plasma exposure. Through this plasma treatment, the device exhibited a threshold voltage shift of 3.1 V in the positive direction, an increase of 50 mS/mm in trans conductance, a degraded off-state performance and a larger gate leakage current compared with that of the reference device without a plasma treatment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.8-14
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• 2011

The optimal geometry of the gate field plate in AlGaN/GaN-on-Si HEMT has been proposed using two-dimensional device simulation to achieve a high breakdown voltage for a given gate-to-drain distance. It was found that the breakdown voltage was drastically enhanced due to the reduced electric field at the gate corner when a gate field plate was employed. The electric field distribution at the gate corner and the field plate edge was investigated as functions of field plate length and insulator thickness. According to the simulation results, the electric field at the gate corner can be successfully reduced even with the field plate length of 1 ${\mu}m$. On the other hand, when the field plate length is too long, the distance between field plate and drain electrode is reduced below a critical level, which eventually lowers the breakdown voltage. The highest breakdown voltage was achieved with the field plate length of 1 ${\mu}m$. According to the simulation results varying the $SiN_x$ film thickness for the fixed field plate length of 1 ${\mu}m$, the optimum thickness range of the $SiN_x$ film was 200 - 300 nm where the electric field strength at the field plate edge counterbalances that of the gate corner.

• Journal of IKEEE
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• v.22 no.3
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• pp.706-711
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• 2018

In this work, we have investigated the characteristics of 4H-SiC metal-oxide-semiconductor (MOS) devices with silicon oxynitride (SiON) insulator using plasma enhanced chemical vapor deposition (PECVD). After post metallization annealing, the trap densities of the fabricated devices decreased significantly. In particular, the device annealed at $500^{\circ}C$ in forming gas ambient exhibited excellent MOS characteristics along with negligible hysteresis, which proved the potential of PECVD SiON as an alternative gate insulator for use in 4H-SiC MOS device.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.281.2-281.2
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• 2016

Two-dimensional van der Waals (2D vdWs) materials have been extensively studied for future electronics and materials sciences due to their unique properties. Among them, black phosphorous (BP) has shown infinite potential for various device applications because of its high mobility and direct narrow band gap (~0.3 eV). In this work, we demonstrate a few-nm thick BP-based nonvolatile memory devices with an well-known poly(vinylidenefluoride-trifluoroethylene) [P(VDF-TrFE)] ferroelectric polymer gate insulator. Our BP ferroelectric memory devices show the highest linear mobility value of $1159cm^2/Vs$ with a $10^3$ on/off current ratio in our knowledge. Moreover, we successfully fabricate the ferroelectric complementary metal-oxide-semiconductor (CMOS) memory inverter circuits, combined with an n-type $MoS_2$ nanosheet transistor. Our memory CMOS inverter circuits show clear memory properties with a high output voltage memory efficiency of 95%. We thus conclude that the results of our ferroelectric memory devices exhibit promising perspectives for the future of 2D nanoelectronics and material science. More and advanced details will be discussed in the meeting.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.318.1-318.1
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• 2016

Hafnium Oxide (HfOx) has been attracted as a promising gate dielectric for replacing SiO2 in gate stack applications. In this paper, Metal-Oxide-Semiconductor (MOS) capacitor with solution processed HfO2 high-k material as a dielectric were fabricated. The solvent using $HfOCl2{\cdot}8H2O$ dissolve in 2-Methoxy ethanol was prepared at 0.3M. The HfOx layers were deposited on p-type silicon substrate by spin-coating at $250^{\circ}C$ for 5 minutes on a hot plate and repeated the same cycle for 5 times, followed by annealing process at 350, 450 and $550^{\circ}C$ for 2 hours. When the annealing temperature was increased from 350 to $550^{\circ}C$, capacitance value was increased from 337 to 367 pF. That was resulted from the higher temperature of HfOx which have more crystallization phase, therefore dielectric constant (k) was increased from 11 to 12. It leads to the formation of dense HfOx film and improve the ability of the insulator layer. We confirm that HfOx layer have a good performance for dielectric layer in MOS capacitors.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.215.2-215.2
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• 2015

We fabricated dual active layer (DAL) thin film transistors (TFTs) with indium tin zinc oxide (ITZO) and indium gallium zinc oxide (IGZO) thin film layers using solution process. The ITZO and IGZO layer were used as the front and back channel, respectively. In order to investigate the bias stress stability of ITZO SAL (single active layer) and ITZO/IGZO DAL TFT, a gate bias stress of 10 V was applied for 1500 s under the dark condition. The SAL TFT composed of ITZO layer shows a poor positive bias stability of ${\delta}VTH$ of 13.7 V, whereas ${\delta}VTH$ of ITZO/IGZO DAL TFT was very small as 2.6 V. In order to find out the evidence of improved bias stress stability, we calculated the total trap density NT near the channel/gate insulator interface. The calculated NT of DAL and SAL TFT were $4.59{\times}10^{11}$ and $2.03{\times}10^{11}cm^{-2}$, respectively. The reason for improved bias stress stability is due to the reduction of defect sites such as pin-hole and pores in the active layer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.44-44
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• 2009

Recently, transparent ZnO-based TFTs have attracted much attention for flexible displays because they can be fabricated on plastic substrates at low temperature. We report the fabrication and characteristics of ZnO channel layers(ZnO TFTs) having different channel thicknesses. The ZnO film were deposited as active channel layers on $Si_3N_4/Ti/SiO_2p$-Si substrates by rf magnetron sputtering at $100\;^{\circ}C$ without additional annealing. Also the Zno thin films deposited at oxygen partial pressures of 40%. ZnO TFTs using a bottom-gate configuration were investigated. The $Si_3N_4$ film were deposited as gate insulator by PE-CVD at $15\;^{\circ}C$. All Processes were processed below $150^{\circ}C$ which is optimal temperature for flexible display and were used dry etching method.