• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1549-1551
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• 2002

현재 게이트 길이가 100nm 이하의 MOSFET 소자를 구현할 때 가장 대두되는 문제인 short channel effect를 억제하는 방법으로 제안된 소자 중 하나가 double gate (DG) silicon-on-insulator (SOI) MOSFET이다. 그러나 DG SOI MOSFET는 두 게이트간의 align과 threshold voltage control 문제가 있다. 본 논문에서는 DG SOI MOSFET에서 이상적으로 게이트가 align된 구조와 back 게이트가 front 게이트보다 긴 non-align된 구조가 subthreshold 동작 영역에서 impact ionization에 미치는 영향에 대해 시뮬레이션을 통하여 비교 분석하였다. 그 결과 게이트가 이상적으로 align된 구조보다 back 게이트가 front 게이트보다 긴 non-align된 구조가 게이트와 드레인이 overlap된 영역에서 impact ionization이 증가하였으며 게이트가 각각 n+ 폴리실리콘과 p+ 폴리실리콘을 가진 소자에서 두 게이트가 같은 work function을 가진 소자보다 높은 impact generation rate을 가짐을 알 수 있었다.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1751-1753
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• 2000

다결정 실리콘 박막 트랜지스터 (poly-Si TFT)의 누설전류를 억제하기 위해 게이트 절연막(gate oxide)의 가장자리에 캐비티(cavity)를 가지는 새로운 구조의 다결정 박막 트랜지스터를 제안하였다. 캐비티는 드레인(drain) 공핍영역(depletion region) 위에 형성되어 드레인 주변에 유도되는 수직전계를 감소시켜 누설전류를 억제하고 소자의 안정성을 향상시킬 수 있다. 본 연구에서 제작된 poly-Si TFT는 기존의 TFT에 비해 온-오프 전류비가 향상되었고 전기적 스트레스 후의 문턱전압 변화가 작음을 확인하였다.

• Transactions on Electrical and Electronic Materials
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• v.2 no.4
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• pp.30-32
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• 2001

In this paper, a new silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) is proposed to improve the latch-up performance without current path underneath the n$^{+}$ cathode region. The improvement of latch-up performance is verified using the two- dimensional simulator MEDICI and the simulation results on the latch-up current density are 4468 A/cm2 for the proposed LIGBT and 1343 A/$\textrm{cm}^2$ for the conventional LIGBT. The proposed SOI LIGBT exhibits 3 times larger latch-up capability than the conventional SOI LIGBT.T.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.598-601
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• 1999

There is currently considerable interest in the applications of conjugated polymers, oligomers and small molecules for thin-film electronic devices. Organic materials have potential advantages to be utilized as semiconductors in field effect transistor and light emitting didoes. In this study, Pentacene thin film transistors(TFTs) were fabricated on glass substrate. Aluminum and Gold wei\ulcorner used fur the gate and source/drain electrodes. Silicon dioxde was deposited as a gate insulator by PECVD and patterned by R.I.E. The semiconductor layer of pentacene was thermally evaporated in vaccum at a pressure of about 10$^{-8}$ Torr and a deposition rate 0.3$\AA$/sec. The fabricated devices exhibited the field-effect mobility as large as 0.07cm$^2$/Vs and on/off current ratio larger than 10$^{7}$

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.9-11
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• 2000

To increase the device linearities and the breakdown-voltages of FETs, Al$\sub$0.25/ Ga$\sub$0.75/AS / In$\sub$0.25/Ga$\sub$0.75/As / Partially doped channel FET(DCFET) structures are proposed. The metal- insulator -semiconductor (MIS) like structures show the high gate-drain breakdown voltage(-20 V) and high linearities. The devices showed the small ripple of the current cut-off frequency and the power cut-off frequency over the wide bias range.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.1200-1203
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• 2004

We investigated the molecular aligning capability of a polymer layer containing ceramic nanoparticles which can be used as a gate insulator of organic thin-film transistors (OTFTs). Because of the enhanced dielectric properties arising from the nanoparticles and molecular aligning properties of the polymer, the composite layer provides excellent mobility characteristics of the OTFTs.

• Proceedings of the Korean Vacuum Society Conference
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• 2005.02a
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• pp.61-61
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• 2005

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1273-1276
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• 2007

We provide a newly developed dry etching process for the fabrication of ZnO-based oxide TFTs. The etching characteristics of ZnO (active layer) and $Al_2O_3$ (gate insulator) thin films were systematically investigated when the etching gas mixtures and their mixing ratios were varied in the heliconplasma etching system.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.718-722
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• 2006

The dependence of n-channel 2 shot SLS poly-Si TFT characteristics on the DOS (density of states) parameters was investigated by using a device simulation. Device performances were most sensitive to the DOS of poly-Si/gate insulator (GI) interface and poly-Si active layer. Deep level states at the poly-Si/GI interfaces strongly affect the subthreshold slope.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1178-1181
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• 2006

We fabricated a flexible OTFT(organic thin film transistor) backplane for the electrophoretic display. The backplane was composed of $128{\times}96pixels$ on the Polyethylene Naphthalate substrate in which each pixel had one OTFT. The OTFTs employed bottom contact structure and used the cross-linked polyvinylphenol for gate insulator and pentacene for active layer