• 한국진공학회지
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• 제13권3호
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• pp.99-102
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• 2004

유기 절연층을 사용한 유기 박막 트랜지스터의 특성 향상을 위해 절연층 표면에 Ar플라즈마 처리를 하였다. 플라즈마 처리는 절연체 표면의 화학적, 물리적 특성 변화를 통해 그 후에 이어지는 활성층 성막시 분자들의 결정성을 향상시키기 위한 방법이다. 활성층으로 사용된 물질은 pentacene이며, 절연층으로 사용된 물질은 PVP(poly-vinyl-phenol)이다. Pentacene는 약 $10^{-6}$ Torr에서 0.5 $\AA$/sec의 속도로, PVP는 spin coating법에 의해 각각 성막되었다. 형성된 절연층을 일정 시간동안 H플라즈마 처리 한 후 각 소자의 전기적 특성을 측정하여 표면처리에 의한 특성 변화를 살펴보았다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 추계학술대회 논문집 학회본부 C
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• pp.455-457
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• 2000

In this work the electrical characteristics of organic TFTs with the semiconductor-insulator interfaces, where the gate dielectrics were treated by the two methods which are the deposition of Octadecyltrichlorosilane (OTS) on the insulator and rubbing the insulator surface. Pentacene is used as an active semiconducting layer. The semiconductor layer of pentacene was thermally evaporated in vacuum at a pressure of about $2{\times}10^{-7}$ Torr and at a deposition rate of $0.3{\AA}/sec$. Aluminum and gold were used for the gate and source/drain electrodes. OTS is used as a self-alignment layer between $SiO_2$ and pentacene. The gate dielectric surface was rubbed before pentacene is deposited on the insulator. In order to confirm the changes of the surface morphology the atomic force microscopy (AFM) was utilized. The characteristics of the fabricated TFTs are measured to clarify the effects of the surface treatment.

• Journal of information and communication convergence engineering
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• 제2권2호
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• pp.93-96
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• 2004

The a-Si:H TFT using ferroelectric of $SrTiO_3$ as a gate insulator is fabricated on glass. Dielectric characteristics of ferroelectric are superior to $SiO_2$ and $Si_{3}N_{4}$. Ferroelectric increases on-current, decreases threshold voltage of TFT and also improves breakdown characteristics. The a-SiN:H has optical band gap of 2.61 eV, retractive index of 1.8∼2.0 and resistivity of $10^{13}$~$10^{15}$ $\Omega$cm, respectively. Insulating characteristics of ferroelectrics are excellent because dielectric constant of ferroelectric is about 60∼100 and breakdown strength is over 1MV/cm. TFT using ferroelectric has channel length of 8∼20 $\mu\textrm{m}$ and channel width of 80∼200 $\mu\textrm{m}$. And it shows that drain current is 3.4$\mu\textrm{A}$ at 20 gate voltage, $I_{on}$/$I_{off}$ is a ratio of $10^5$~$10^8$ and $V_{th}$ is 4∼5 volts, respectively. In the case of TFT without ferroelectric, it indicates that the drain current is 1.5 $\mu\textrm{A}$ at 20 gate voltage and $V_{th}$ is 5∼6 volts. With the improvement of the ferroelectric thin film properties, the performance of TFT using this ferroelectric has advanced as a gate insulator fabrication technology is realized.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.395-395
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• 2007

We report on the fabrication of soluble pentacene-based thin-film transistors (TFTs) that consist of $NiO_x$, poly-vinyl phenol (PVP), and Ni for the source-drain (SID) electrodes, gate dielectric, and gate electrode, respectively. The $NiO_x$ SID electrodes of which the work function is well matched to that of soluble pentacene are deposited on a soluble pentacenechannel by sputter deposited of NiO powder and show a moderately low but still effective transmittance of ~65% in the visible range along with a good sheet resistance of ${\sim}40{\Omega}/{\square}$. The maximum saturation current of our soluble pentacene-based TFT is about $15{\mu}A$ at a gate bias of -40showing a high field effect mobility of $0.06cm^2/Vs$ in the dark, and the on/off current ratio of our TFT is about $10^4$. It is concluded that jointly adopting $NiO_x$ for the S/D electrodes and PVP for gate dielectric realizes a high-quality soluble pentacene-based TFT.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2002년도 International Meeting on Information Display
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• pp.184-187
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• 2002

In this work, the electrical characteristics of organic thin film transistors with the stacked organic gate insulators have been studied. PVP(Polyvinylphenol) and polystyrene were used as gate insulating materials. Both the high dielectric constant of PVP and better insulating capability of polystyrene were compensatorily adopted in two different stacking orders of PVP-polystyrene and polystyrene-PVP. The output characteristics of the device with the stacked gate insulator showed substantial improvement compared with those of the devices with either PVP or polystyrene gate insulator: Furthermore, these stacked organic gate insulators can differently affect the TFT characteristics with the stacking orders. The electrical properties of TFTs with organic gate insulators stacked in different orders are discussed.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제50권4호
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• pp.161-168
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• 2001

Organic thin film transitors(TFTs) are of interest for use in broad area electronic applications. For example, in active matrix liquid crystal displays(AMLCDs), organic TFTs would allow the use of inexpensive, light-weight, flexible, and mechanically rugged plastic substrates as an alternative to the glass substrates needed for commonly used hydrogenated amorphous silicon(a-Si:H). Recently pentacene TFTs with carrier field effect, mobility as large as 2 $cm^2V^{-1}s^{-1}$ have been reported for TFTs fabricated on silicon substrates, and it is higher than that of a-Si:H. But these TFTs are fabricated on silicon wafer and $SiO_2$ was used as a gate insulator. $SiO_2$ deposition process requires a high insulator which is polyimide and photo acryl. We investigated trasfer and output characteristics of the thin film transistors having active layer of pentacene. We calculated field effect mobility and on/off ratio from transfer characteristics of pentacene thin film transistor, and measured IR absorption spectrum of polymide used as the gate dielectric layer. It was found that using the photo acryl as a gate insulator, threshold voltage decreased from -12.5 V to -7 V, field effect mobility increased from 0.012 $cm^2V^{-1}s^{-1}$ to 0.039 $cm^2V^{-1}s^{-1}$ , and on/off current ratio increased from $10^5\;to\;10^6$. It seems that TFTs using photo acryl gate insulator is apt to form channel than TFTs using polyimide gate insulator.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.318.1-318.1
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• 2016

Hafnium Oxide (HfOx) has been attracted as a promising gate dielectric for replacing SiO2 in gate stack applications. In this paper, Metal-Oxide-Semiconductor (MOS) capacitor with solution processed HfO2 high-k material as a dielectric were fabricated. The solvent using $HfOCl2{\cdot}8H2O$ dissolve in 2-Methoxy ethanol was prepared at 0.3M. The HfOx layers were deposited on p-type silicon substrate by spin-coating at $250^{\circ}C$ for 5 minutes on a hot plate and repeated the same cycle for 5 times, followed by annealing process at 350, 450 and $550^{\circ}C$ for 2 hours. When the annealing temperature was increased from 350 to $550^{\circ}C$, capacitance value was increased from 337 to 367 pF. That was resulted from the higher temperature of HfOx which have more crystallization phase, therefore dielectric constant (k) was increased from 11 to 12. It leads to the formation of dense HfOx film and improve the ability of the insulator layer. We confirm that HfOx layer have a good performance for dielectric layer in MOS capacitors.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.58-61
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• 2001

Metal-insulator-semiconductor (MIS) C-V properties with high dielectric AIN thin films showed no hysteresis and good interface properties. The dielectric constant of the AIN film calculated from the capacitance at the accumulation region in the capacitance-voltage(C-V) characteristics was about 8. The C-V characteristics of MFIS capacitor showed a hysteresis loop due to the ferroelectric nature of the LiNbO$_3$ thin films. Typical dielectric constant value of LiNbO$_3$ film of MFIS device was about 23. The memory window width was about 1.2V at the gate voltage of $\pm$5 V ranges. Typical gate leakage current density of the MFIS structure was the order of 10$^{-9}$ A/cm$^2$ at the range of within $\pm$500 kV/cm. The ferroelectric capacitors showed no polarization degradation up to about 10$^{11}$ switching cycles when subjected to symmetric bipolar voltage pulse(peak-to-peak 8V, 50% duty cycle) in the 500kHz.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 C
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• pp.1924-1926
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• 2005

Poly(methyl methacrylate) (PMMA) is one of the promising representive of polymer gate dielectric for its high resistivity and sutible dielectric constant. PMMA (Mw=96700) films were prepared on p-Si by spin coating method. PMMA were coated compactively and flatly as observes by AFM. MIS(Al/PMMA/p-Si) structure was made and capacitance-voltage (C-V) and current-voltage (I-V) measurements were done with PMMA films for repeated annealing cycles at $100^{\circ}C$. 1-V measured at various delay times $(0{\sim}20sec)$ showed little change and the absence of hysteresis in the I-V characteristics with delay times, which eliminate the possibility of deep traps in the PMMA films. The observed thermal stability, smooth surfaces, dielectric constant, I-V behavior implies PMMA formed by spin coating can be used as an efficient gate dielectric layer in OTFTs.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 춘계학술대회 논문집 전자세라믹스 센서 및 박막재료 반도체재료 일렉트렛트 및 응용기술
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• pp.180-183
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• 2000

Beginning with a brief introduction on near 100 nm or below CMOS devices, this paper addresses novel devices for future sub-100 nm CMOS. First, key issues such as gate materials, gate dielectric, source/drain, and channel in Si bulk CMOS devices are considered. CMOS devices with different channel doping and structure are introduced by explaining a figure of merit. Finally, novel device structures such as SOI, SiGe, and double-gate devices will be discussed for possible candidates for sub-100 nm CMOS.