• The Journal of Society for e-Business Studies
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• v.9 no.1
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• pp.209-220
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• 2004

If protocol has fast operations and short key length, it can be efficient user authentication protocol. Lenstra and Verheul proposed XTR. XTR have short key length and fast computing speed. Therefore, this can be used usefully in complex arithmetic. In this paper, to design efficient user authentication protocol we used a subgroup of Galois Field to problem domain. Proposed protocol does not use GF(p/sup 6/) that is existent finite field, and uses GF(p²) that is subgroup and solves problem. XTR-ElGamal based user authentication protocol reduced bit number that is required when exchange key by doing with upside. Also, proposed protocol provided easy calculation and execution by reducing required overhead when calculate. In this paper, we designed authentication protocol with y/sub i/ = g/sup b.p/sup 2(i-1)//ㆍv mol q, 1(equation omitted) 3 that is required to do user authentication.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.6
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• pp.736-743
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• 2020

Modular multiplication is one of the most important arithmetic operations in public-key cryptography such as elliptic curve cryptography (ECC) and RSA, and the performance of modular multiplier is a key factor influencing the performance of public-key cryptographic hardware. An efficient hardware implementation of word-based Montgomery modular multiplication algorithm is described in this paper. Our modular multiplier was designed to support eleven field sizes for prime field GF(p) and binary field GF(2k) as defined by SEC2 standard for ECC, making it suitable for lightweight hardware implementations of ECC processors. The proposed architecture employs pipeline scheme between the partial product generation and addition operation and the modular reduction operation to reduce the clock cycles required to compute modular multiplication by 50%. The hardware operation of our modular multiplier was demonstrated by FPGA verification. When synthesized with a 65-nm CMOS cell library, it was realized with 33,635 gate equivalents, and the maximum operating clock frequency was estimated at 147 MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.255-258
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• 2004

Efficient finite field operation in the elliptic curve (EC) public key cryptography algorithm, which attracts much of latest issues in the applications in information security, is very important. Traditional serial finite multipliers root from Mastrovito's serial multiplication architecture. In this paper, we adopt the polynomial basis and propose a new finite field multiplier, inducing numerical expressions which can be applied to exhibit 3 times as much performance as the Mastrovito's. We described the proposed multiplier with HDL to verify and evaluate as a proper hardware IP. HDL-implemented serial GF (Galois field) multiplier showed 3 times as fast speed as the traditional serial multiplier's adding only Partial-sum block in the hardware.

• Journal of information and communication convergence engineering
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• v.3 no.4
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• pp.201-204
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• 2005

Twofish is a 128-bit block cipher that accepts a variable-length key up to 256 bits. The cipher is a 16­round Feistel network with a bijective F function made up of four key-dependent 8-by-8-bit S-boxes, a fixed 4­by-4 maximum distance separable matrix over Galois Field$(GF (2^8)$, a pseudo-Hadamard transform, bitwise rotations, and a carefully designed key schedule. In this paper, the Twofish is modeled in VHDL and simulated. Hardware implementation gives much better performance than software-based approaches.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.6B
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• pp.984-990
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• 2010

In Current Digital $C^3$ Devices(Communication, Computer, Consumer electronic devices), Reed-Solomon encoder is essentially used. For example we should use RS encoder in DSP LSI of CDMA Mobile and Base station modem, in controller LSI of DVD Recorder and that of computer memory(HDD or SSD memory). In this paper, we propose new economical multiplierless (also without divider) RS encoder design method. The encoder has Arbitrary parity positions.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.3 s.357
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• pp.61-67
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• 2007

In Reed Solomon decoder, when there are more than 4 error symbols, we usually use Chien search machine to find those error positions. In this case, classical method requires complex and relatively slow digital circuitry to implement it. In this paper we propose New fast and cost effective Chien search machine design method using Galois Subfield transformation. Example is given to show the method is working well. This new design can be applied to the case where there are more than 5 symbol errors in the Reed-Solomon code word.

• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2702-2704
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• 2003

본 논문은 전력선통신시스템 (Power Line Communications)을 위한 초고속 오류정정 부호화기 회로에 관한 설계방법론과 회로의 동작속도, 회로복잡성과 레이턴시에 직접적으로 기여하는 핵심 GF (Galois Field) 연산기들의 역할 및 이들의 설계결과에 관해 설명한다. 특히, 이러한 설계방법에 충실한 오류정정 부호화기회로는 입출력 병렬구조의 세미-시스톨릭 (Semi-systolic) 아키텍처를 갖는 고속의 내부 핵심 GF 연산기회로들을 채택함으로써 고속 연산을 가능토록 한다. 최적화된 GF곱셈연산기를 기반으로 설계되어진 리드-솔로몬 (Reed-Solomon) 오류정정 부호화기는 전력선 채널상에서 데이터를 전송 시 발생되는 연집오류들을 효과적으로 복원하도록 하는 대표적인 부호화기로 이미 존재하는 다른 회로들에 비해 동작속도, 회로의 복잡성, 및 레이턴시 측면에서 그 성능이 월등히 뛰어나므로, 실제 초고속 전력선 통신시스템의 설계 및 구현 시 효과적으로 이용될 수 있다.

• Journal of Korea Multimedia Society
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• v.16 no.5
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• pp.577-590
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• 2013

Shamir's (k,n)-threshold secret sharing scheme is not secure against cheating by attacker because the signature of participants is omitted. To prevent cheating, many schemes have been proposed, and a proactive secret sharing is one of those. The proactive secret sharing is a method to update shares in the secret sharing scheme at irregular intervals. In this paper, a proactive image secret sharing scheme over $GF(2^8)$ is proposed for the first time. For the past 30 years, Galois field operation is widely used in order to perform the efficient and secure bit operation in cryptography, and the proposed scheme with update phase of shadow image over $GF(2^8)$) at irregular intervals provides the lossless and non-compromising of secret image. To evaluate security and efficiency of images (i.e. cover and shadow images) distortion between the proposed scheme and the previous schemes, embedding capacity and PSNR are compared in experiments. The experimental results show that the performances of the embedding capacity and image distortion ratio of the proposed scheme are superior to the previous schemes.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.328-332
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• 2006

Efficient finite field operation in the elliptic curve (EC) public key cryptography algorithm, which attracts much of latest issues in the applications in information security, is very important. Traditional serial finite multipliers root from Mastrovito's serial multiplication architecture. In this paper, we adopt the polynomial basis and propose a new finite field multiplier, inducing numerical expressions which can be applied to exhibit 3 times as much performance as the Mastrovito's. We described the proposed multiplier with HDL to verify and evaluate as a proper hardware IP. HDL-implemented serial GF (Galois field) multiplier showed 3 times as fast speed as the traditional serial multiplier's adding only partial-sum block in the hardware. So far, there have been grossly 3 types of studies on GF($2^m$) multiplier architecture, such as serial multiplication, array multiplication, and hybrid multiplication. In this paper, we propose a novel approach on developing serial multiplier architecture based on Mastrovito's, by modifying the numerical formula of the polynomial-basis serial multiplication. The proposed multiplier architecture was described and implemented in HDL so that the novel architecture was simulated and verified in the level of hardware as well as software.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.4C
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• pp.191-196
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• 2011

In this paper, we propose a design method of Reed-Solomon (23, 17) decoder for UWB using direct decoding method. The direct decoding algorithm is more efficient for the case of relatively small error correction capability. The proposed decoder requires only 9 $GF(2^m)$ multipliers in obtaining the error-locator polynomial and the error-evaluator polynomial, whereas other decoders need about 20 multipliers. Thus, the attractive feature of this decoder is its remarkable simplicity from the point of view of hardware implementation. Futhermore, the proposed decoder has very simple control circuit and short decoding delay. Therefore this decoder can be implemented by simple hardware and also save buffer memory which stores received sequence.