• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.60.1-60.1
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• 2011

비정질 indium-gallium-zinc-oxide (a-IGZO)는 thin film transistor (TFT)에 적용되는 대표적인 active layer로써 높은 이동도를 갖고, 도핑 농도의 제어가 용이하며 낮은 온도에서도 대면적에 증착할 수 있는 특성을 가지고 있다. 특히 저온에서 대면적 증착이 가능한 장점을 갖고 있어 LCD 분야뿐만 아니라 다양한 분야에서 상용화하려는 연구가 시도되고 있다. a-IGZO를 구성하는 물질 중에 이동도에 중요한 역할을 미치는 In은 대표적인 투명전극물질인 indium-tin oxide (ITO)에서 고전류 구동에 의한 확산이 널리 알려져 이에 대한 증명과 개선을 위한 연구가 진행되고 있다. 보고된 결과에 따르면 device에 지속적인 구동 전압을 가했을 때 In이 유기층로 확산되어 organic light emitting diode(OLED)의 성능을 저하시키는 것으로 알려져 있다. 따라서, a-IGZO에서도 고전류 구동에 의한 indium의 이동이 필수불가결하다고 판단된다. 본 연구에서는 a-IGZO TFT에 고전압 구동을 반복적으로 시행함으로써 발생하는 전기적 특성의 변화를 확인하였고, 동일한 소자의 전극과 채널 사이의 계면에서 In 분포를 energy dispersive spectrometer (EDS)로 관찰하여 In 분포와 전기적 특성 간의 상관관계에 대해 연구하였다.

• Nuclear Engineering and Technology
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• v.52 no.7
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• pp.1537-1544
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• 2020

Molecular dynamics (MD) simulations were conducted to investigate the temperature effects on the primary damage in gallium nitride (GaN) material. Five temperatures ranging from 300 K to 900 K were studied for 10 keV Ga primary knock-on atom (PKA) with inject direction of [0001]. The results of MD simulations showed that threshold displacement energy (E_d) was affected by temperatures and at higher temperature, it was larger. The evolutions of defects under various temperatures were similar. However, the higher temperature was found to increase the peak number, peak time, final time and recombination efficiency while decreasing the final number. With regard to clusters, isolated point defects and little clusters were common clusters and the fraction of point defects increased with temperature for vacancy clusters, whereas it did not appear in the interstitial clusters. Finally, at each temperature, the number of Ga interstitial atoms was larger than that of N and besides that, there were other different results of specific types of split interstitial atoms.

• International Journal of Internet, Broadcasting and Communication
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• v.12 no.2
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• pp.30-36
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• 2020

We demonstrated a successful fabrication of 4" Gallium Nitride (GaN)/Diamond High Electron Mobility Transistors (HEMTs) incorporated with Inner Slot Via Hole process. We made in manufacturing technology of 4" GaN/Diamond HEMT wafers in a compound semiconductor foundry since reported [1]. Wafer thickness uniformity and wafer flatness of starting GaN/Diamond wafers have improved greatly, which contributed to improved processing yield. By optimizing Laser drilling techniques, we successfully demonstrated a through-substrate-via process, which is last hurdle in GaN/Diamond manufacturing technology. To fully exploit Diamond's superior thermal property for GaN HEMT devices, we include Aluminum Nitride (AlN) barrier in epitaxial layer structure, in addition to conventional Aluminum Gallium Nitride (AlGaN) barrier layer. The current collapse revealed very stable up to Vds = 90 V. The trapping behaviors were measured Emission Microscope (EMMI). The traps are located in interface between Silicon Nitride (SiN) passivation layer and GaN cap layer.

• The Korean Journal of Ceramics
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• v.5 no.4
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• pp.404-408
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• 1999

Gallium doped zinc oxide(GZO) films were deposited on soda-lime glass substrates without substrate heating $(T_s<50^{\circ}C$) by dc planar magnetron sputtering using GZO ceramic oxide targe with different inert gas (Ar, or Ne). For the GZO films deposited under different total gas pressure $(P_{tot})$, structural and electrical properties were investigated by XRD and Hall effect measurements. Crystallinity of GZO films deposited using Ar was degraded with increase in $(P_{tot})$, suggesting that it was heavily affected by kinetic energy of sputtered Zn particles$(PA_{zn})$ arriving at substrate surface. Whereas, crystallinity of GZO films deposited at lower Ptot than 3.0 Pa using Ne gas was degraded with decrease in $(P_{tot})$. This degradation was considered to be result of film damage caused by the bombardment of high-energy neutrals ($Ne^{\circ}$). On the basis of a hard sphere collision processes, the average final energy of particles (sputtered Zn, $Ar^{\circ}$and $Ne^{\circ}$)arriving at substrate surface were estimated.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.3-3
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• 2010

We investigated the influence of the indium content on the threshold voltage ($V_{th}$) shift of sol-gel-derived indium-gallium-zinc oxide (IGZO) thin film transistors (TFTs). Surplus indium composition ratio into IGZO decreases the value of $V_{th}$ of IGZO TFTs showed huge $V_{th}$ shift in the negative direction. $V_{th}$ shift decreases from 10 to -28.2V as Indium composition ratio is increased. Because the free electron density is increased according to variation of the Indium composition ratio.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.10
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• pp.1209-1215
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• 1988

A space charge effect at the doped silicon semiconductor/organic solvent ($C_6H_6$, $CH_3OH$, $C_2H_5OH$) interfaces and a mechanism for two reversals of zeta potentials at the undoped polycrystalline gallium arsenide semiconductor/electrolyte (NaCl, KCl, KI solution) interfaces has been qualitatively analyzed using microelectrophoresis measurements. It has been found that the space charge effect in the organic solvents can be neglected and the two reversals of zeta potentials depend on surface states, specific adsorption, electronegativity and size of specifically adsorbed ions at the undoped polycrystalline gallium arsenide/electrolyte interfaces. The position of shear plane of colloidal semiconductors is a fixed distance from the surface and is almost or exactly coincides with the outer Helmholtz plane (OHP).

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.217-220
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• 2001

CaN(gallium nitride) MODFET(modulation doped field effect transistor) large signal model was studied using Modified Materka-Kacprzak large signal MODFET model. using the Dambrine's method［3, at 45MHz-40㎓, Measured S-parameter and DC characteristics. based on measuring results, small signal parameter extraction was conducted. by the cold FET［4］method, measured parasitic elements were de-embedding. Extracted small signal parameters were modeled using modified Materka model, a sort of fitting function reproduce measuring results. to confirm conducted large signal modeling, modeled GaN MODFET's DC, S-parameter and Power characteristics were compared to measured results, respectively. by results were represented comparatively agreement, this paper showed that modified Materka model was useful in the GaN MODFET large signal modeling.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.10 no.5
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• pp.71-78
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• 2011

In this paper, we describe the design and implementation of a high efficiency and broad-band Class-J mode power amplifier using gallium nitride(GaN) high-electron mobility transistor(HEMT). The matching circuit of proposed class-J mode power amplifier for 2nd harmonic impedance designed to provide pure reactance alone. The measurement results show that output power of $40{\pm}1$ dBm, power-added efficiency of 50%, and drain efficiency of 60% for a continuous wave signal at 1.4 to 2.6 GHz.

• Journal of Electrical Engineering and Technology
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• v.10 no.3
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• pp.1131-1137
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• 2015

Gallium nitride (GaN) is a promising material for next-generation high-power applications due to its wide bandgap, high breakdown field, high electron mobility, and good thermal conductivity. From a structure point of view, the vertical device is more suitable to high-power applications than planar devices because of its area effectiveness. However, it is challenging to obtain a completely upright vertical structure due to inevitable sidewall slope in anisotropic etching of GaN. In this letter, we design and analyze the enhancement-mode n-channel vertical GaN MOSFET with variation of sidewall gate angle by two-dimensional (2D) technology computer-aided design (TCAD) simulations. As the sidewall slope gets closer to right angle, the device performances are improved since a gradual slope provides a leakage current path through the bulk region.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.224-224
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• 2010

최근 반도체 나노막대의 구조적, 광학적 특성을 이용한 새로운 개념의 광학 및 전자 소자 개발을 위한 연구가 활발히 진행되고 있다. 기존의 반도체 나노막대는 gold를 촉매로 하여 성장한 것이 대부분이었지만, gold 촉매는 다른 물질에 빠르게 확산되기 때문에 반도체 특성에 좋지 않은 영향을 미친다. 이러한 이유로 aluminum이나 titanium과 같은 물질을 gold 촉매 대신 사용하거나 촉매를 사용하지 않는 성장 방법에 관한 이슈들이 주목받고 있다. 본 연구에서는 금속 촉매 물질을 사용하지 않고 반도체 나노막대 성장을 시도하였다. 금속 촉매 없이 반도체 나노막대를 성장하는 것은 반도체 특성에 악영향을 미치지 않을 뿐더러, 공정 과정이 용이하다는 장점 때문에 최근 많이 시도되고 있다. 본 실험에서는 Molecular Beam Epitaxy (MBE) 방법을 이용하여 (100) GaAs 기판 위에 GaAs 나노막대를 성장하였다. 금속 촉매 없이 반도체 나노막대를 성장하기 위해 에칭된 $SiO_2$ 층을 이용하였다. GaAs 기판 위에 형성된 35nm 두께의 $SiO_2$를 20:1 BOE 용액에서 10초 간 에칭하면 $SiO_2$상에 pinhole을 형성하는데 이것이 gallium과 반응하면 나노막대 성장을 유도하는 seed가 만들어져 촉매를 사용하지 않고도 나노막대 성장이 가능하다. GaAs 나노막대 성장을 위해 BOE 에칭 조건, gallium incubation time 유무, GaAs 나노막대 성장온도, galiium과 arsenic의 성분 비율, GaAs 양 등을 변화시켜 실험하였고 이렇게 성장된 나노막대가 SEM image 상에서 관찰되었다.