• Title/Summary/Keyword: Gain correction

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Theoretical Investigation of First-order and Second-order Polarization-mode Dispersion Tolerance on Various Modulation Formats in 40 Gb/s Transmission Systems with FEC Coding

  • Jang, Ho-Deok;Kim, Kyoung-Soo;Lee, Jae-Hoon;Jeong, Ji-Chai
    • Journal of the Optical Society of Korea
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    • v.13 no.2
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    • pp.227-233
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    • 2009
  • We investigated the polarization-mode dispersion (PMD) tolerance for 40Gb/s non-return to zero (NRZ), duobinary NRZ, return to zero (RZ), carrier-suppressed RZ (CS-RZ), and duobinary-carrier-suppressed RZ (DCS-RZ) modulation formats with a forward error correction (FEC) coding. The power penalty has been calculated as a measure of the system performance due to PMD. After comparison of the PMD tolerance of various modulation formats, our results suggest that RZ signals have the best tolerance against the effect of first-order PMD only. The duobinary NRZ modulation format is most resilient to PMD when both first- and second-order PMD are considered. However, the duobinary NRZ modulation format is the most sensitive to the incident angle of the input signal to a fiber axis in the presence of first- and second-order PMD, leading to incident angle-dependent power penalty. The coding gain by FEC can cope with the power penalties induced by first- and second-order PMD up to a DGD value of 16ps.

The Optimal Compensation Gain Algorithm Using Variable Step for Buck-type Active Power Decoupling Circuits (벅-타입 능동 전력 디커플링을 위한 가변 스텝을 적용한 최적 보상 이득 알고리즘)

  • Baek, Ki-Ho;Kim, Seung-Gwon;Park, Sung-Min
    • The Transactions of the Korean Institute of Power Electronics
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    • v.23 no.2
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    • pp.121-128
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    • 2018
  • This work proposes a simple control method of a buck-type active power decoupling circuit that can minimize the ripple values in the dc link voltage. The proposed method utilizes a simplified duty calculation method and an optimal compensation gain tracking algorithm with variable-step approach. Thus, the dc link voltage ripple can be effectively reduced through the proposed method along with rapid response in tracking the optimum compensation gain. Moreover, the proposed method has better dynamic responses in the load fluctuation or abnormal situation. MATLAB/Simulink simulation and hardware-in-the-loop-simulation(HILS)-based experimental results are presented to validate the effectiveness of the proposed control method.

Fuzzy Methods for the design of Digital Controllers with Intelligent Calibration (지능형 자동 보정화 디지털 제어기 설계를 위한 퍼지 기법)

  • 나승유;박민상
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 1998.10a
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    • pp.187-190
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    • 1998
  • The values of physical components of the plants and controllers as well as the relevant environmental conditions change in time, thus the output performance can be deteriorated during the operating span of the system. Naturally the duty of calibration or the prevention of performance deterioration due to excessive component sensitivity should be provided to the control system. The proposed controller, whenever necessary, measures the open-loop and close-loop characteristics, and then calculates the offset and sensor gain correction values based on the prepared standard measurements It is applied to the control of a flexible link system with the gain and offset calibration problems in the light sensor module for position to show the applicability. In this paper, we propose a digital controller which has the capability of calibration gain and offset adjustment using fuzzy methods.

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Improved BP-NN Controller of PMSM for Speed Regulation

  • Feng, Li-Jia;Joung, Gyu-Bum
    • International journal of advanced smart convergence
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    • v.10 no.2
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    • pp.175-186
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    • 2021
  • We have studied the speed regulation of the permanent magnet synchronous motor (PMSM) servo system in this paper. To optimize the PMSM servo system's speed-control performance with disturbances, a non-linear speed-control technique using a back-propagation neural network (BP-NN) algorithm forthe controller design of the PMSM speed loop is introduced. To solve the slow convergence speed and easy to fall into the local minimum problem of BP-NN, we develope an improved BP-NN control algorithm by limiting the range of neural network outputs of the proportional coefficient Kp, integral coefficient Ki of the controller, and add adaptive gain factor β, that is the internal gain correction ratio. Compared with the conventional PI control method, our improved BP-NN control algorithm makes the settling time faster without static error, overshoot or oscillation. Simulation comparisons have been made for our improved BP-NN control method and the conventional PI control method to verify the proposed method's effectiveness.

Scene-based Nonuniformity Correction Algorithm Based on Temporal Median Filter

  • Geng, Lixiang;Chen, Qian;Qian, Weixian;Zhang, Yuzhen
    • Journal of the Optical Society of Korea
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    • v.17 no.3
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    • pp.255-261
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    • 2013
  • Scene-based nonuniformity correction techniques for infrared focal-plane arrays have been widely considered as a key technology, and various algorithms have been proposed to compensate for fixed-pattern noise. However, the existed algorithms' capability is always restricted by the problems of convergence speed and ghosting artifacts. In this paper, an effective scene-based nonuniformity correction method is proposed to solve these problems. The algorithm is an improvement over the constant statistics method and a temporal median is utilized with the Gaussian kernel to estimate the nonuniformity parameters. Also theoretical analysis is conducted to demonstrate that effective ghosting artifacts elimination and superior convergence speed can be obtained with the proposed method. Finally, the performance of the proposed technique is tested with infrared image sequences with simulated nonuniformity and with infrared imagery with real nonuniformity. The results show the proposed method is able to estimate each detector's gain and to offset reliably and that it performs better in increasing convergence speed and reducing ghosting artifacts compared with the conventional techniques.

High-Performance Low-Complexity Iterative BCH Decoder Architecture for 100 Gb/s Optical Communications (100 Gb/s급 광통신시스템을 위한 고성능 저면적 반복 BCH 복호기 구조)

  • Yang, Seung-Jun;Yeon, Jaewoong;Lee, Hanho
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.7
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    • pp.140-148
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    • 2013
  • This paper presents a iterative Bose-Chaudhuri-hocquenghem (i-BCH) code and its high-speed decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability. The proposed 6-iteration i-BCH code structure with interleaving method allows the decoder to achieve 9.34 dB net coding gain performance at $10^{-15}$ decoder output bit error rate to compensate for serious transmission quality degradation. The proposed high-speed i-BCH decoder architecture is synthesized using a 90-nm CMOS technology. It can operate at a clock frequency of 430 MHz and achieve a data processing rate of 100 Gb/s. Thus, it has potential applications in next generation forward error correction (FEC) schemes for 100 Gb/s optical communications.

A 1.8 V 40-MS/sec 10-bit 0.18-㎛ CMOS Pipelined ADC using a Bootstrapped Switch with Constant Resistance

  • Eo, Ji-Hun;Kim, Sang-Hun;Kim, Mun-Gyu;Jang, Young-Chan
    • Journal of information and communication convergence engineering
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    • v.10 no.1
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    • pp.85-90
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    • 2012
  • A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

Outcome and Efficacy of Height Gain and Sagittal Alignment after Kyphoplasty of Osteoporotic Vertebral Compression Fractures

  • Lee, Tae-One;Jo, Dae-Jean;Kim, Sung-Min
    • Journal of Korean Neurosurgical Society
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    • v.42 no.4
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    • pp.271-275
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    • 2007
  • Objective : Although a significant correction of local kyphosis has been reported previously, only a few studies have investigated whether this correction leads to an improved overall sagittal alignment. The study objective was to determine whether an improvement in the local kyphotic angle improves the overall sagittal alignment. We examined and compared the effects of thoracic and lumbar level kyphoplasty procedures on local versus overall sagittal alignment of the spine. Methods : Thirty-eight patients with osteoporotic vertebral compression fractures who showed poor response to conventional, palliative medical therapy underwent single-level kyphoplasty. The pertinent clinical data of these patients, from June 2006 to November 2006, were reviewed retrospectively. We measured preoperative and postoperative vertebral body heights, which were classified as anterior, middle, or posterior fractured vertebral body heights. Furthermore, the local and overall sagittal angles after polymethylmethacrylate deposition were measured. Results : More height was gained at the thoracic level, and the middle vertebral height regained the most. A significant local kyphosis correction was observed at the fractured level, and the correction at larger spanning segments decreased with the distance from the fractured level. Conclusion : The inflatable balloon kyphoplasty procedure was the most effective in regaining the height of the thoracic fractured vertebra in the middle vertebral body. The kyphosis correction by kyphoplasty was mainly achieved in the fractured vertebral body. Sagittal angular correction decreased with an increase in the distance from the fractured vertebra. No significant improvement was observed in the overall sagittal alignment after kyphoplasty. Further studies in a larger population are required to clarify this issue.

A CMOS Image Sensor with Analog Gamma Correction using a Nonlinear Single Slope ADC (비선형 단일 기울기 ADC를 사용하여 아날로그 감마 보정을 적용한 CMOS 이미지 센서)

  • Ham Seog-Heon;Han Gunhee
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.1 s.343
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    • pp.65-70
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    • 2006
  • An image sensor has limited dynamic range while the human eye has logarithmic response over wide range of light intensity. Although the sensor gain can be set high to identify details in darker area on the image, this results in saturation in brighter area. The gamma correction is essential to fit the human eye response. However, the digital gamma correction degrades image quality especially for darker area on the image due to the limited ADC resolution and the dynamic range. This Paper proposes a CMOS image sensor (CIS) with a nonlinear analog-to-digital converter (AU) which performs analog gamma correction. The CIS with the proposed nonlinear analog-to-digital conversion scheme was fabricated with a $0.35{\mu}m$ CMOS process. The analog gamma correction using the proposed nonlinear ADC CIS provides the 2.2dB peak-signal-to-noise-ratio(PSM) improved image qualify than conventional digital gamma correction. The PSNR of the image obtain from the digital gamma correction is 25.6dB while it is 27.8dB for analog gamma correction. The PSNR improvement over digital gamma correction is about $28.8\%$.

Optimum Blind Control to Prevent Glare Considering Potential Time Error (잠재적 시간 오차에 따른 현휘의 발생 방지를 위한 최적 블라인드 제어)

  • Seong, Yoon-Bok
    • Journal of the Korean Solar Energy Society
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    • v.32 no.2
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    • pp.74-86
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    • 2012
  • For the improvement of environmental comfort in the buildings with the blind control, the objective of this study is to prevent the direct glare caused by the daylight inlet. During the process of solar profile prediction, time are significant factors that may cause error and glare during the blind control. This research proposes and evaluates the correction and control method to minimize prediction error. For the local areas with different longitude and local standard meridian, error occurred in the process of the time conversion from local standard time to apparent solar time. In order to correct error in time conversion, apparent solar time should be recalculated after adjusting the day of year and the equation of time. To solve the problems by the potential time errors, control method is suggested to divide the control sections using the calibrated fitting-curve and this method is verified through simulations. The proposed correction and control method, which considered potential time errors by loop lop leap years, could solve the problems about direct glare caused by daylight inlet on the work-plane according to the prediction errors of solar profile. And also these methods could maximize daylight inlet and solar heat gain, because the blocked area on windows could be minimized.