• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2004.10a
• /
• pp.1376-1379
• /
• 2004

This study is designed integration and control system of GaAs bonding system consisted of multi-processing using DeviceNet and GEM-Protocol. Developing bonding system is composed of resin coating, pre-baking pre-aligner, bonding, material handler(flip robot), and wafer cassette, etc. This system has process-fluent of each a process and share information using GEM-protocol. This study devised virtual bonding simulator to control and to monitor bonding system efficiently. Also we can verify optimizing of system previously through a virtual bonding simulator.

• Journal of the Semiconductor & Display Technology
• /
• v.20 no.4
• /
• pp.125-129
• /
• 2021

We investigated the electronic property and atomic structure for chalcopyrite (CH) Al_xGa_1-xAs semiconductor by using first-principles FPLMTO method. The CH-Al_xGa_1-xAs exhibits a p-type semiconductor with a direct band-gap. For low Al concentration unoccupied hole-carriers are induced, but for high Al concentration it is formed a localized bonding or anti-bonding state below Fermi level. The hybridization of Al(3s)-Ga(4s, or 4p) is larger than that of Al(3s)-As(4s, or 4p). And the Al film on As-terminated surface, Al/AsGa(001), is more energetically favorable one than that on Ga-terminated (001) surface. Consequently, the band-gap of CH-Al_xGa_1-xAs system increases exponentially with increasing Al concentration. The change of lattice parameter is shown two different configurations with increasing Al concentration. The calculated lattice parameters for CH-Al_xGa_1-xAs system are compared to the experimental ones of zinc-blend GaAs and AlAs.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2005.10a
• /
• pp.427-431
• /
• 2005

In this study, 6' GaAs wafer bonding system is designed and optimized to bond 6 inches device wafer and material wafer. Bonding process is performed in vacuum environment and resin is used to bond two wafers. Vacuum module and double heating mechanisms are adopted to minimize wafer warpage and void. Structure and heat transfer analysis, et al of the core modules review the designed mechanisms are very effective in performance improvement. As a result, high productivity (tack time cut-down) and stabilized process can be obtained by reducing breakage failure of wafer.

• Journal of the Korean Vacuum Society
• /
• v.20 no.1
• /
• pp.22-29
• /
• 2011

An infrared thermographic imaging module of [$320{\times}256$] focal-plane array (FPA) based on [InAs/GaSb] strained-layer superlattice (SLS) was fabricated, and its images were demonstrated. The p-i-n device consisted of an active layer (i) of 300-period [13/7]-ML [InAs/GaSb]-SLS and a pair of p/n-electrodes of (60/115)-period [InAs:(Be/Si)/GaSb]-SLS. FTIR photoresponse spectra taken from a test device revealed that the peak wavelength (${\lambda}_p$) and the cutoff wavelength (${\lambda}_{co}$) were approximately $3.1/2.7{\mu}m$ and $3.8{\mu}m$, respectively, and it was confirmed that the device was operated up to a temperature of 180 K. The $30/24-{\mu}m$ design rule was applied to single pixel pitch/mesa, and a standard photolithography was introduced for [$320{\times}256$]-FPA fabrication. An FPA-ROIC thermographic module was accomplished by using a $18/10-{\mu}m$ In-bump/UBM process and a flip-chip bonding technique, and the thermographic image was demonstrated by utilizing a mid-infrared camera and an image processor.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.4 no.3
• /
• pp.189-195
• /
• 2004

A 10 Gb/s limiting amplifier IC with the emitter area of $1.5{\times}10{\mu}m^2$ for optical transmission system was designed and fabricated with a AIGaAs/GaAs HBTs technology. In this stud)', we evaluated fine pitch bump using WL-CSP (Wafer Level-Chip Scale Packaging) instead of conventional wire bonding for interconnection. For this we developed WL-CSP process and formed fine pitch solder bump with the $40{\mu}m$ diameter and $100{\mu}m$ pitch on bonding pad. To study the effect of WL-CSP, electrical performance was measured and analyzed in wafer and package module using WL-CSP. In a package module, clear and wide eye diagram openings were observed and the riselfall times were about 100ps, and the output" oltage swing was limited to $600mV_{p-p}$ with input voltage ranging from 50 to 500m V. The Small signal gains in wafer and package module were 15.56dB and 14.99dB respectively. It was found that the difference of small signal gain in wafer and package module was less then 0.57dB up to 10GHz and the characteristics of return loss was improved by 5dB in package module. This is due to the short interconnection length by WL-CSP. So, WL-CSP process can be used for millimeter wave GaAs MMIC with the fine pitch pad.