• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1199-1200
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• 2011

The low voltage DC-DC Converter(LDC) is used for various electronic devices of electric vehicle. Depending on the growth of the car, the capacity of power conversion circuits must be increased. They have to provide the high efficiency and the high load capacity. The phase shift controlled full-bridge converter can be designed for LDC. The operating characteristics are considered through by simulation.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.413-417
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• 2004

Recent experiments have shown the 'size effects' in micro/nano scale. But the classical plasticity theories can not predict these size dependent deformation behaviors because their constitutive models have no characteristic material length scale. The Mechanism - based Strain Gradient(MSG) plasticity is proposed to analyze the non-uniform deformation behavior in micro/nano scale. The MSG plasticity is a multi-scale analysis connecting macro-scale deformation of the Statistically Stored Dislocation(SSD) and Geometrically Necessary Dislocation(GND) to the meso-scale deformation using the strain gradient. In this research we present a study of nano-indentation by the MSG plasticity. Using W. D. Nix and H. Gao s model, the analytic solution(including depth dependence of hardness) is obtained for the nano indentation , and furthermore it validated by the experiments.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.239-242
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• 2005

A high speed address recovery technique for AC plasma display Panel(PDP) is proposed. By removing the GND switching operation, the recovery speed can be increased and switching loss due to GND switch also becomes to be reduced. The proposed method is able to perform load-adaptive operation by controlling the voltage level of energy recovery capacitor, which prevents increasing inefficient power consumption caused by circuit loss during recovery operation. Thus, the technique shows the minimum address power consumption according to various displayed images, different from Prior methods operating in fixed mode regardless of images. Test results with 50" HD single-scan PDP(resolution = 1366$\times$768) show that less than 350ns of recovery time is successfully accomplished and about 54% of the maximum power consumption can be reduced, tracing minimum power consumption curves.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2011.04a
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• pp.257-260
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• 2011

마이크로 스케일에서 다결정 재료의 소성 거동을 살펴볼 때, 결정의 geometrically necessary dislocation(GND) 효과에 의한 소성 구배(plastic gradient)의 고려는 재료의 소성 거동에 큰 영향을 미칠 수 있다. 본 연구에서는 소성 구배의 영향을 살펴보기 위하여 다결정 고체(polycrystalline solids)의 거동을 유한요소해석을 이용하여 살펴보았다. 소성 구배의 영향을 살펴보기 위하여 구배 경화 계수(gradient hardness coefficient)와 먼 거리 변형률에 대한 재료 길이 변수(material length parameter)가 사용되었다. 재료 길이 변수의 영향을 살펴보기 위해, 재료 길이 변수의 차이에 따른 다결정 고체의 거동을 분석하였다. 또한 소성 구배 효과의 고려와 재료 길이 변수의 변화에 따라서 다결정 고체 내부에 위치한 단결정이 받는 영향을 살펴보았다. 재료 길이 변수에 따라 결정이 받는 영향을 비교하여, GND에 의한 다결정 고체 거동의 영향을 확인하였다.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2005.05a
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• pp.192-200
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• 2005

A high speed address recovery technique for AC plasma display panel(PDP) is proposed. By removing the GND switching operation, the recovery speed can be increased and switching loss due to GND switch also becomes to be reduced. The proposed method is able to perform load-adaptive operation by controlling the voltage level of energy recovery capacitor, which prevents increasing inefficient power consumption caused by circuit loss during recovery operation. Thus, th e technique shows the minimum address power consumption according to various displayed images, different from prior methods operating in fixed mode regardless of images. Test results with 50' HD single- scan PDP(resolution : $1366{\times}768$) show that less than 350ns of recovery time is successfully accomplished and about $54\%$ of the maximum power consumption can be reduced, tracing minimum power consumption curves.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.7
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• pp.689-697
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• 2007

This thesis suggests ways on how to enhance handset radiation power under head phantom condition. Generally, peak EIRP(Effective Isotropic Radiated Power) is used to measure the radiation performance. TRP is more effective to represent indication of mobile radiation performance in the field than EIRP. In this case, we measure the TRP as an index of radiation power. The factors which effect TRP are antenna length, antenna position, folder angle and ground connection method. More detailed analysis is performed over these items. Significant item is ground connection method between main PCB and folder GND. Using the FPCB we connect main GND to folder GND through the hinge near the antenna. The result is that TRP attenuation is decreased about 5 dB under head phantom condition.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.10
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• pp.979-986
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• 2013

In this paper, a TVS diode which is commonly used as a ESD protector in wireless communication devices could cause antenna wireless sensitivity to decrease has been analyzed. When a smartphone doesn't have enough space to place many components, there would be its speaker near antenna area. In order to protect ESD coming through the speaker there also could be a TVS within antenna GND area. Digital audio signal which was sent to speaker and CDMA RF communication signal coupled from antenna was mixed by TVS. And this leakage current running through TVS resulted in decrease of antenna wireless sensitivity. The results of various experiments can be explained using circuit simulation. Following works will give us some insights that can reduce unwanted summation of digital and RF signal due to nonlinearity of ESD protectors.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.9
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• pp.535-540
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• 2017

The changes in the electrical characteristics of CMOS ICs due to coupling with a narrow-band electromagnetic wave were analyzed in this study. A magnetron (3 kW, 2.45 GHz) was used as the narrow-band electromagnetic source. The DUT was a CMOS logic IC and the gate output was in the ON state. The malfunction of the ICs was confirmed by monitoring the variation of the gate output voltage. It was observed that malfunction (self-reset) and destruction of the ICs occurred as the electric field increased. To confirm the variation of electrical characteristics of the ICs due to the narrow-band electromagnetic wave, the pin-to-pin resistances (Vcc-GND, Vcc-Input1, Input1-GND) and input capacitance of the ICs were measured. The pin-to-pin resistances and input capacitance of the ICs before exposure to the narrow-band electromagnetic waves were $8.57M{\Omega}$ (Vcc-GND), $14.14M{\Omega}$ (Vcc-Input1), $18.24M{\Omega}$ (Input1-GND), and 5 pF (input capacitance). The ICs exposed to narrow-band electromagnetic waves showed mostly similar values, but some error values were observed, such as $2.5{\Omega}$, $50M{\Omega}$, or 71 pF. This is attributed to the breakdown of the pn junction when latch-up in CMOS occurred. In order to confirm surface damage of the ICs, the epoxy molding compound was removed and then studied with an optical microscope. In general, there was severe deterioration in the PCB trace. It is considered that the current density of the trace increased due to the electromagnetic wave, resulting in the deterioration of the trace. The results of this study can be applied as basic data for the analysis of the effect of narrow-band high-power electromagnetic waves on ICs.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.6
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• pp.1287-1292
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• 2012

In this paper, a dual polarization patch antenna operates at the wide bandwidth of 1.525GHz~1.665GHz was designed and fabricated. To obtain the wide bandwidth and high gain, increased height of air floor from GND was applied, and to get wide band axial ratio and high gain, parasitic patch was applied. The simulation and measurement showed good agreements, the VSWR was less than 1.9 at the frequency bandwidth, the return loss was less than -10dB, and the LHCP(Left Hand Circular Polarization) and RHCP(Right Hand Circular Polarization) isolation was less than -13dB at the frequency bandwidth.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.93-98
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• 2004

A low power SRAM using elevated source level memory cells is proposed to save the write power of SRAM. It reduces the swing voltages of the bit lines and data bus by elevating the source level of the memory cells from GND to $V_{T}$ and lowering the precharge level of the bit lines and data bus from $V_{DD}$ to $V_{DD}$ - $V_{T}$. It saves the write power of SRAM without area overhead and speed degradation. An SRAM with 8K${\times}$32bits is fabricated in a 0.25um CMOS process. It saves 45% of the power in write cycles at 300MHz with 2.5V. The maximum operating frequency is 330MHz.