• Title/Summary/Keyword: GF(2$^n$)

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CYCLIC CODES FROM THE FIRST CLASS TWO-PRIME WHITEMAN'S GENERALIZED CYCLOTOMIC SEQUENCE WITH ORDER 6

  • Kewat, Pramod Kumar;Kumari, Priti
    • Bulletin of the Korean Mathematical Society
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    • v.56 no.2
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    • pp.285-301
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    • 2019
  • Let $p_1$ and $p_2$ be two distinct odd primes with gcd($p_1-1$, $p_2-1$) = 6. In this paper, we compute the linear complexity of the first class two-prime Whiteman's generalized cyclotomic sequence (WGCS-I) of order d = 6. Our results show that their linear complexity is quite good. So, the sequence can be used in many domains such as cryptography and coding theory. This article enrich a method to construct several classes of cyclic codes over GF(q) with length $n=p_1p_2$ using the two-prime WGCS-I of order 6. We also obtain the lower bounds on the minimum distance of these cyclic codes.

A Hardware Implementation of the Underlying Field Arithmetic Processor based on Optimized Unit Operation Components for Elliptic Curve Cryptosystems (타원곡선을 암호시스템에 사용되는 최적단위 연산항을 기반으로 한 기저체 연산기의 하드웨어 구현)

  • Jo, Seong-Je;Kwon, Yong-Jin
    • Journal of KIISE:Computing Practices and Letters
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    • v.8 no.1
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    • pp.88-95
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    • 2002
  • In recent years, the security of hardware and software systems is one of the most essential factor of our safe network community. As elliptic Curve Cryptosystems proposed by N. Koblitz and V. Miller independently in 1985, require fewer bits for the same security as the existing cryptosystems, for example RSA, there is a net reduction in cost size, and time. In this thesis, we propose an efficient hardware architecture of underlying field arithmetic processor for Elliptic Curve Cryptosystems, and a very useful method for implementing the architecture, especially multiplicative inverse operator over GF$GF (2^m)$ onto FPGA and futhermore VLSI, where the method is based on optimized unit operation components. We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed and inversion speed has been improved 150 times, 480 times respectively compared with the thesis presented by Sarwono Sutikno et al. [7]. The designed underlying arithmetic processor can be also applied for implementing other crypto-processor and various finite field applications.

Design and Implementation of an Efficient Fair Off-line E-Cash System based on Elliptic Curve Discrete Logarithm Problem

  • Lee, Manho;Gookwhan Ahn;Kim, Jinho;Park, Jaegwan;Lee, Byoungcheon;Kim, Kwangjo;Lee, Hyuckjae
    • Journal of Communications and Networks
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    • v.4 no.2
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    • pp.81-89
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    • 2002
  • In this paper, we design and implement an efficient fair off-line electronic cash system based on Elliptic Curve Discrete Logarithm Problem (ECDLP), in which the anonymity of coins is revocable by a trustee in case of dispute. To achieve this, we employ the Petersen and Poupard s electronic cash system [1] and extend it by using an elliptic curve over the finite field GF($2^n$). This naturally reduces message size by 85% compared with the original scheme and makes a smart card to store coins easily. Furthermore, we use the Baek et al. s provably secure public key encryption scheme [2] to improve the security of electronic cash system. As an extension, we propose a method to add atomicity into new electronic cash system. To the best of our knowledge, this is the first result to implement a fair off-line electronic cash system based on ECDLP with provable security.

Properties of Pepsin Inhibitor Produced by Actinomycetes sp. GF 155-2 (Actinomyces sp. GF155-2가 생산하는 Pepsin 저해물질의 성질)

  • 박석규;성낙계;노종수;김양우;조영숙
    • Microbiology and Biotechnology Letters
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    • v.18 no.5
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    • pp.496-500
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    • 1990
  • When pepsin was used at a concentration of 8 mglml for hydrolysis of 0.02% casein, inhibitory activity of this inhibitor was proportional to a inhibitor concentration of 20 ${\mu}g$/ml, and fifty percent inhibition ($IC_{50}$) was observed to be 15 ${\mu}g$/ml. The inhibitor was pH-stable at pH range of 5-9 at $100^{\circ}C$ for 10 minutes and thermo-stable at pH 7.0 at $100^{\circ}C$ to give 100% activity for 20 minutes. The formation of pepsin-inhibitor complex was confirmed by sephadex 6-25 gel filtration and type of inhibition was determined as non-competitive inhibition by Lineweaver-Burk plot. The inhibitor strongly inhibited acid proteases such as pepsin and renin, and it was soluble in methanol very well. On TLC analysis of silicagel 60 using various sohent systems, the inhibitor gave a single spot at Rf range 0.4-0.6. From the result of IR spectrum and color reaction (Rydon-Smith, Biuret), this inhibitor was considered as peptide substance. Melting point and elemental contents were 220-$230^{\circ}C$, and C 50.61%-H 8.02%-N 9.34% (found), respectively.

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NONEXISTENCE OF SOME EXTREMAL SELF-DUAL CODES

  • Han, Sun-Ghyu;Lee, June-Bok
    • Journal of the Korean Mathematical Society
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    • v.43 no.6
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    • pp.1357-1369
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    • 2006
  • It is known that if C is an [24m + 2l, 12m + l, d] selfdual binary linear code with $0{\leq}l<11,\;then\;d{\leq}4m+4$. We present a sufficient condition for the nonexistence of extremal selfdual binary linear codes with d=4m+4,l=1,2,3,5. From the sufficient condition, we calculate m's which correspond to the nonexistence of some extremal self-dual binary linear codes. In particular, we prove that there are infinitely many such m's. We also give similar results for additive self-dual codes over GF(4) of length n=6m+1.

Improved Decoding Algorithm on Reed-Solomon Codes using Division Method (제산방법에 의한 Reed-Solomon 부호의 개선된 복호알고리듬)

  • 정제홍;박진수
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.30A no.11
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    • pp.21-28
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    • 1993
  • Decoding algorithm of noncyclic Reed-Solomon codes consists of four steps which are to compute syndromes, to find error-location polynomial, to decide error-location, and to solve error-values. There is a decoding method by which the computation of both error-location polynomial and error-evaluator polynimial can be avoided in conventional decoding methods using Euclid algorithm. The disadvantage of this method is that the same amount of computation is needed that is equivalent to solve the avoided polynomial. This paper considers the division method on polynomial on GF(2$^{m}$) systematically. And proposes a novel method to find error correcting polynomial by simple mathematical expression without the same amount of computation to find the two avoided polynomial. Especially. proposes the method which the amount of computation to find F (x) from the division M(x) by x, (x-1),....(x--${\alpha}^{n-2}$) respectively can be avoided. By applying the simple expression to decoding procedure on RS codes, propses a new decoding algorithm, and to show the validity of presented method, computer simulation is performed.

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Design of an Efficient Bit-Parallel Multiplier using Trinomials (삼항 다항식을 이용한 효율적인 비트-병렬 구조의 곱셈기)

  • 정석원;이선옥;김창한
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.13 no.5
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    • pp.179-187
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    • 2003
  • Recently efficient implementation of finite field operation has received a lot of attention. Among the GF($2^m$) arithmetic operations, multiplication process is the most basic and a critical operation that determines speed-up hardware. We propose a hardware architecture using Mastrovito method to reduce processing time. Existing Mastrovito multipliers using the special generating trinomial p($\chi$)=$x^m$+$x^n$+1 require $m^2$-1 XOR gates and $m^2$ AND gates. The proposed multiplier needs $m^2$ AND gates and $m^2$+($n^2$-3n)/2 XOR gates that depend on the intermediate term xn. Time complexity of existing multipliers is $T_A$+( (m-2)/(m-n) +1+ log$_2$(m) ) $T_X$ and that of proposed method is $T_X$+(1+ log$_2$(m-1)+ n/2 ) )$T_X$. The proposed architecture is efficient for the extension degree m suggested as standards: SEC2, ANSI X9.63. In average, XOR space complexity is increased to 1.18% but time complexity is reduced 9.036%.

Design of an Adaptive Reed-Solomon Decoder with Varying Block Length (가변 블록길이를 갖는 적응형 리드솔로몬 복호기의 설계)

  • Song, Moon-Kyou;Kong, Min-Han
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.4C
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    • pp.365-373
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    • 2003
  • In this paper, we design a versatle RS decoder which can decode RS codes of any block length n as well as any message length k, based on a modified Euclid's algorithm (MEA). This unique feature is favorable for a shortened RS code of any block length it eliminates the need to insert zeros before decoding a shortened RS code. Furthermore, the value of error correcting capability t can be changed in real time at every codeword block. Thus, when a return channel is available, the error correcting capability can be adaptiverly altered according to channel state. The decoder permits 4-step pipelined processing : (1) syndrome calculation (2) MEA block (3) error magnitude calculation (4) decoder failure check. Each step is designed to form a structure suitable for decoding a RS code with varying block length. A new architecture is proposed for a MEA block in step (2) and an architecture of outputting in reversed order is employed for a polynomial evaluation in step (3). To maintain to throughput rate with less circuitry, the MEA block uses not only a multiplexing and recursive technique but also an overclocking technique. The adaptive RS decoder over GF($2^8$) with the maximal error correcting capability of 10 has been designed in VHDL, and successfully synthesized in a FPGA.

Development of Hardware Modules for Elliptic Curve Cryptosystems based on Binary Field and Optimal Extension Field (이진체와 확장체에 기반한 타원곡선 암호시스템의 하드웨어 모듈 개발)

  • 전향남;정필규;김동규
    • Proceedings of the Korea Multimedia Society Conference
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    • 2003.11a
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    • pp.158-161
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    • 2003
  • 1985년 N. Koblitz와 V. Miller가 각각 독립적으로 제안한 타원곡선 암호시스템(ECC : Elliptic Curve Cryptosystems)은 유한체 위에서 정의된 타원곡선 군에서의 이산대수 어려움에 기초한다. 타원곡선 암호시스템은 다른 공개키 시스템에 비해 보다 짧은 길이의 키만으로도 동일한 수준의 안전도를 유지할 수 있다는 장점으로 인하여, 스마트카드나 모바일 시스템 등에서와 같이 메모리와 처리능력이 제한된 하드웨어에도 이식 가능한 장점이 있다. 본 논문에서는 타원곡선 암호시스템에 필요한 유한체 연산을 이진체(Binary Finite Field)인 GF(2$^{193}$ )과 OEF(Oprimal Extension Field) 상에서 VHDL 언어를 사용하여 구현을 하였고 각 연산의 성능을 비교하였다.

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A Continuous Versatile Reed-Solomon Decoder with Variable Code Rate and Block Length (가변 부호율과 블록 길이를 갖는 연속 가변형 리드솔로몬 복호기)

  • 공민한;송문규
    • Proceedings of the IEEK Conference
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    • 2003.07a
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    • pp.549-552
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    • 2003
  • In this paper, an efficient architecture of a versatile Reed-Solomon (RS) decoder is designed, where the message length k as well as the block length n can be variable. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm(MEA). A new architecture for the MEA is designed for variable values of error correcting capability t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive and the overclocking technique. The decoder can decode a codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications due to its versatility. A versatile RS decoder over GF(2$^{8}$ ) having the error-correcting capability of up to 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

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