Design of an Efficient Bit-Parallel Multiplier using Trinomials |
정석원
(고려대학교 정보보호대학원)
이선옥 (고려대학교 정보보호대학원) 김창한 (세명대학교 인터넷 정보학부) |
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VLSI architectures for Computation in Galois Fields
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A New architecture for a parallel finite field multiplier with low complexity based on composite fields
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Mastrovito multiplier for general irreducible polynomials
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Low-complexity bit parallel canonicaland normal basis multipliers for a class of finite fields
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Masrovito Multiplier for All Trinomial
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Efficient VLSI Arthitectures for Bit parallel Computation in Galois fields
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VLSI architectures for multiplication over finite field
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