• Title/Summary/Keyword: GATE simulation

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Simulation of 4H-SiC MESFET for High Power and High Frequency Response

  • Chattopadhyay, S.N.;Pandey, P.;Overton, C.B.;Krishnamoorthy, S.;Leong, S.K.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.3
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    • pp.251-263
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    • 2008
  • In this paper, we report an analytical modeling and 2-D Synopsys Sentaurus TCAD simulation of ion implanted silicon carbide MESFETs. The model has been developed to obtain the threshold voltage, drain-source current, intrinsic parameters such as, gate capacitance, drain-source resistance and transconductance considering different fabrication parameters such as ion dose, ion energy, ion range and annealing effect parameters. The model is useful in determining the ion implantation fabrication parameters from the optimization of the active implanted channel thickness for different ion doses resulting in the desired pinch off voltage needed for high drain current and high breakdown voltage. The drain current of approximately 10 A obtained from the analytical model agrees well with that of the Synopsys Sentaurus TCAD simulation and the breakdown voltage approximately 85 V obtained from the TCAD simulation agrees well with published experimental results. The gate-to-source capacitance and gate-to-drain capacitance, drain-source resistance and trans-conductance were studied to understand the device frequency response. Cut off and maximum frequencies of approximately 10 GHz and 29 GHz respectively were obtained from Sentaurus TCAD and verified by the Smith's chart.

A Case Study on Developing Automotive Part(Housing) by Filling and Solidification Analysis (유동 및 응고해석을 이용한 자동차용 부품(하우징)개발에 대한 사례연구)

  • Jeong, Byoung-Guk;Kwon, Hong-Kyu
    • Journal of Korean Society of Industrial and Systems Engineering
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    • v.38 no.1
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    • pp.44-51
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    • 2015
  • When manufacturing die casting mold, generally, the casting layout design should be considered based on the relations of injection system, casting condition, gate system, and cooling system. According to the various relations of the conditions, the location of product defects was differentiated. High-qualified products can be manufactured as those defects are controlled by the proper modifications of die casting mold with keeping the same conditions. In this research, Computer Aided Engineering (CAE) simulation was performed with the several layout designs in order to optimize the casting layout design of an automotive part (Housing). In order to apply them into the production die-casting mold, the simulation results were analyzed and compared carefully. With the filling process, internal porosities caused by air entrapments were predicted and also compared with the modification of the gate system and overflow. With the solidification analysis, internal porosities occurring during the solidification process were predicted and also compared with the modified gate system. The simulation results were also applied into the production die-casting mold in order to compare the results and verify them with the real casting samples.

Gate Workfunction Optimization of a 32 nm Metal Gate MOSFET for Low Power Applications

  • Oh Yong-Ho;Kim Young-Min
    • Journal of Electrical Engineering and Technology
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    • v.1 no.2
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    • pp.237-240
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    • 2006
  • The feasibility of a midgap metal gate is investigated for a 32 nm MOSFET for low power applications. The midgap metal gate MOSFET is found to deliver $I_{on}$ as high as a bandedge gate if a proper retrograde channel is used. An adequate design of the retrograde channel is essential to achieve the performance requirement given in the ITRS roadmap. A process simulation is also run to evaluate the feasibility of the necessary retrograde profile in manufacturing environments. Based on the simulated result, it is found that any subsequent thermal process should be tightly controlled to retain transistor performance, which is achieved using the retrograde doping profile. Also, the bandedge gate MOSFET is determined be more vulnerable to the subsequent thermal processes than the midgap gate MOSFET. A guideline for gate workfunction $(\Phi_m)$ is suggested for the 32 nm MOSFET.

A New GTO Driving Technique for Faster Switching (고속 스윗징을 위한 새로운 GTO 구동기법)

  • Kim, Young-Seok;Seo, Beom-Seok;Hyun, Dong-Seok
    • The Transactions of the Korean Institute of Electrical Engineers
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    • v.43 no.2
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    • pp.244-250
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    • 1994
  • This paper presents the design of a new turn-off gate drive circuit for GTO which can accomplish faster turn-off switching. The major disadvantage of the conventional turn-off gate drive technique is that it has a difficulty in realizing high negative diS1GQT/dt because of VS1RGM(maximum reverse gate voltage) and stray inductances of turn-off gate drive circuit[1~2]. The new trun-off gate drive technique can overcome this problem by adding another turn-off gate drive circuit to the conventional turn-off gate drive circuit. Simulation and experimental results of the new turn-off gate drive circuit in conjunction with chopper circuit verify a faster turn-off switching performance.

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Casting Layout Design Using CAE Simulation : Automotive Part(Oil Pan_BR2E) (CAE을 이용한 주조방안설계 : 자동차용 부품(오일팬_BR2E))

  • Kwon, Hong-kyu
    • Journal of Korean Society of Industrial and Systems Engineering
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    • v.40 no.1
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    • pp.35-40
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    • 2017
  • A most important progress in civilization was the introduction of mass production. One of main methods for mass production is die-casting molds. Due to the high velocity of the liquid metal, aluminum die-casting is so complex where flow momentum is critical matter in the mold filling process. Actually in complex parts, it is almost impossible to calculate the exact mold filling performance with using experimental knowledge. To manufacture the lightweight automobile bodies, aluminum die-castings play a definitive role in the automotive part industry. Due to this condition in the design procedure, the simulation is becoming more important. Simulation can make a casting system optimal and also elevate the casting quality with less experiment. The most advantage of using simulation programs is the time and cost saving of the casting layout design. For a die casting mold, generally, the casting layout design should be considered based on the relation among injection system, casting condition, gate system, and cooling system. Also, the extent or the location of product defects was differentiated according to the various relations of the above conditions. In this research, in order to optimize the casting layout design of an automotive Oil Pan_BR2E, Computer Aided Engineering (CAE) simulation was performed with three layout designs by using the simulation software (AnyCasting). The simulation results were analyzed and compared carefully in order to apply them into the production die-casting mold. During the filling process with three models, internal porosities caused by air entrapments were predicted and also compared with the modification of the gate system and overflows. With the solidification analysis, internal porosities occurring during the solidification process were predicted and also compared with the modified gate system.

Mo-tip Field Emitter Array having Modified Gate Insulator Geometry (변형된 게이트 절연막 구조를 갖는 몰리브덴 팁 전계 방출 소자)

  • Ju, Byeong-Kwon;Kim, Hoon;Lee, Nam-Yang
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.49 no.1
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    • pp.59-63
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    • 2000
  • For the Mo-tip field emitter array, the method by which the geometrical structure of the gate insulator wall could be modified in order to improve field emission properties(turn-on voltage and gate leakage current). The device having a gate insulator of complex shape, which means the combined geometrical structure with round shape made by wet etching and vertical shape made by dry etching processes, was fabricated and the field emission properties of the three kinds of devices were compared. As a result, the electric field applied to tip apex could be increased and gate leakage current could be decreased by employing the gate insulator having geometrical wall structure of mixed shape. Finally, the obtained empirical results were analyzed by simulation of electric field distribution at/near the tip apex and gate insulator using SNU-FEAT simulator.

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Analysis of Electrical Characteristics of Shield Gate Power MOSFET for Low on Resistance (차폐형 게이트 구조를 갖는 전력 MOSFET의 전기적 특성 분석에 관한 연구)

  • Kang, Ey-Goo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.30 no.2
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    • pp.63-66
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    • 2017
  • This research was about shielded trench gate power MOSFET for low voltage and high speed. We used T-CAD tool and carried out process and device simulation for exracting design and process parameters. The exracted parameters was used to design shieled and conventional trench gate power MOSFET. And The electrical characteristics of shieled and conventional trench gate power MOSFET were compared and analyzed for their power device applications. As a result of analyzing electrical characteristics, the recorded breakdown voltages of both devices were around 120 V. The electric distributions of shielded and conventional trench gate power MOSFET was different. But due to the low voltage level, the breakdown voltage was almost same. And the other hand, the threshold voltage characteristics of shielded trench gate power MOSFET was superior to convention trench gate power MOSFET. In terms of on resistance characteristics, we obtained optimal oxied thickness of $3{\mu}m$.

Characteristics analysis of Sub-50nm Double Gate MOSFET (Sub-50nm Double Gate MOSFET의 특성 분석)

  • 김근호;고석웅;이종인;정학기
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2002.11a
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    • pp.486-489
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    • 2002
  • In this paper, we have investigated characteristics of sub-50nm double gate MOSFET. From I-V characteristics, we obtained =510$\mu$A/${\mu}{\textrm}{m}$ at VMG=VDS=1.5V and VSG=3.0V. Then, the transconductance is 111$\mu$A/V, subthreshold slope is 86mV/dec and DIBL (Drain Induced Barrier Lowering) is 51.3mV. Also, we have presented that TCAD simulator is suitable for device simulation.

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A Study to Reduce the Waiting Time in the Toll Gate (고속도로 매표방법 개선에 관한 연구)

  • 조면식
    • Journal of the Korea Society for Simulation
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    • v.3 no.1
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    • pp.99-105
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    • 1994
  • Most of the companies are forced to cut down the manufacturing cost to survive in the competitive environment. Among others, material distribution cost alone takes substantial portion of the total manufacturing cost. In this study, we investigate the waiting phenomenon in the toll gate and propose a new toll booth layout to reduce the waiting time, thereby reduce the total material distribution cost. SIMAN, a simulation language, is employed to evaluate the proposed layout. The experimental results show that the layout reduces the waiting time significantly. Furthermore, the result indicates that determination of the intermediate buffer space affects the performance of the proposed layout.

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Optimization of Gate Location for Melt Flow Balancing in Injection Mold Cavity By Using Recursive Design Area Reduction Method (설계영역 반복축소법에 의한 사출금형의 수지 유동균형을 위한 게이트 위치 최적화)

  • Park, Jong-Cheon;Lee, Gyu-Seok;Choi, Seong-Il;Kang, Jin-Hyun
    • Journal of the Korean Society of Manufacturing Process Engineers
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    • v.12 no.4
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    • pp.114-122
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    • 2013
  • This study introduces an optimization methodology for the determination of gate location that ensures the melt flow balance within a part cavity of injection mold. A new sequential direct-search scheme based on the recursive reduction of the designer-specified gate design area is developed, and it is integrated with a commercial flow simulation tool for optimization. To quantify the level of melt flow balance, we employ the maximum difference among the fill times for the melt fronts to reach the boundary elements of part cavity as objective function. The proposed methodology is successfully applied in the case study of melt flow balancing in molding of a bar code scanner model. The result shows that the melt flow balance at the optimized gate positions is significantly improved from that for the initial gate position.