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Studies on Computerization of the Korean Libraries (한국 도서관의 컴퓨터 기술 도입에 관한 연구)

  • Chun Myung Sook
    • Journal of the Korean Society for Library and Information Science
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    • v.17
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    • pp.161-201
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    • 1989
  • 1. Introduction Korean society is moving toward an information society in 2000. At present a few Korean libraries are computerized and networks between libraries have yet to be formed. And there is no study done on the computerization of the Korean libraries. Therefore, this study will attempt to find elements that influence the computerization of Korean libraries. This research is composed of the following three parts. 1) Survey on the present status of computerized Korean libraries. 2) The influencing factors for Korean library computerization on the level of organization. 3) The relationship between professionalism and the access to the computer information on the level of librarians. 2. Hypothesis The basic hypothesis of this research is from the theory of the innovation of organization by Moch. He found that the size of the organization, specialization of the staffs, the task differentiation, and decentralization of decision making were the underlying influence for the organizational innovation. From this theory, hypothesis were formulated as follows. 1) The size of the library influences the library computerization. 2) Specialization of the librarians influences the library computerization. 3) Differentiation of the library services influences the library computerization. 4) The decision making process influences the library computerization. 3. Collection of the data Questionnaires were sent to 21 computerized libraries among which were 8 experimental group and 7 other controlled group libraries. Data were collected from April to July 1988. 4. Findings 1) The present status of Korean library computerization. -Korean libraries are computerized mostly in cataloguing. -The computer technology gate-keepers are mainly librarians. -The computerization budgets are not specifically allocated or funded by the organization but librarians made decisions to allocate library budget for the computer application. Gradually, more libraries are being funded specially for library computerization. 2) Factors that influence library computerization. -The size of the western books and the number of western periodical subscription influence the library computerization. -The number of annual book increase influences library computerization. -The number of annual book use influences library computerization. -The number of annual library users does not influences library computerization. - The size of the library budget influences the library computerization. -Librarian's specialization influences the library computerization. -Differentiation of library service influences the library computerization. Information service is positively related to the library computerization while data service is not related to the library computerization. -Decentralization of decision making in library service influences the library computerization.

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Parallel Inverse Transform and Small-sized Inverse Quantization Architectures Design of H.264/AVC Decoder (H.264/AVC 복호기의 병렬 역변환 구조 및 저면적 역양자화 구조 설계)

  • Jung, Hong-Kyun;Cha, Ki-Jong;Park, Seung-Yong;Kim, Jin-Young;Ryoo, Kwang-Ki
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2011.10a
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    • pp.444-447
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    • 2011
  • In this paper, parallel IT(inverse transform) architecture and IQ(inverse quantization) architecture with common operation unit for the H.264/AVC decoder are proposed. By using common operation unit, the area cost and computational complexity of IQ are reduced. In order to take four execution cycles to perform IT, the proposed IT architecture has parallel architecture with one horizontal DCT unit and four vertical DCT units. Furthermore, the execution cycles of the proposed architecture is reduced to five cycles by applying two state pipeline architecture. The proposed architecture is implemented to a single chip by using Magnachip 0.18um CMOS technology. The gate count of the proposed architecture is 14.3k at clock frequency of 13MHz and the area of proposed IQ is reduced 39.6% compared with the previous one. The experimental result shows that execution cycle the proposed architecture is about 49.09% higher than that of the previous one.

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Architecture Design of High Performance H.264 CAVLC Encoder Using Optimized Searching Technique (최적화된 탐색기법을 이용한 고성능 H.264/AVC CAVLC 부호화기 구조 설계 기법)

  • Lee, Yang-Bok;Jung, Hong-Kyun;Kim, Chang-Ho;Myung, Je-Jin;Ryoo, Kwang-Ki
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2011.10a
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    • pp.431-435
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    • 2011
  • This paper presents optimized searching technique to improve the performance of H.264/AVC. The proposed CAVLC encoder uses forward and backward searching algorithm to compute the parameters. By zero-block skipping technique and pipelined scheduling, the proposed CAVLC encoder can obtain better performance. The experimental result shows that the proposed architecture needs only 66.6 cycles on average for each $16{\times}16$ macroblock encoding. The proposed architecture improves the performance by 13.8% than that of previous designs. The proposed CAVLC encoder was implemented using VerilogHDL and synthesized with Megnachip $0.18{\mu}m$ standard cell library. The synthesis result shows that the gate count is about 15.6K with 125Mhz clock frequency.

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Design and Implementation of Adaptive Beam-forming System for Wi-Fi Systems (무선랜 시스템을 위한 적응형 빔포밍 시스템의 설계 및 구현)

  • Oh, Joohyeon;Gwag, Gyounghun;Oh, Youngseok;Cho, Sungmin;Oh, Hyukjun
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.9
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    • pp.2109-2116
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    • 2014
  • This paper presents the implementation and design of the advanced WI-FI systems with beam-forming antenna that radiate their power to the direction of user equipment to improve the overall throughput, contrast to the general WI-FI systems equipped with omni-antenna. The system consists of patch array antenna, DSP, FPGA, and Qualcomm's commercial chip. The beam-forming system on the FPGA utilizes the packet information from Qualcomm's commercial chip to control the phase shifters and attenuators of the patch array antenna. The PCI express interface has been used to maximize the communication speed between DSP and FPGA. The directions of arrival of users are managed using the database, and each user is distinguished by the MAC address given from the packet information. When the system wants to transmit a packet to one user, it forms beams to the direction of arrival of the corresponding user stored in the database to maximize the throughput. Directions of arrival of users are estimated using the received preamble in the packet to make its SINR as high as possible. The proposed beam-forming system was implemented using an FPGA and Qualcommm's commercial chip together. The implemented system showed considerable throughput improvement over the existing general AP system with omni-directional antenna in the multi-user communication environment.

Design and Implementation of Open Service Platform for LBS (LBS를 위한 개방형 서비스 플랫폼의 설계 및 구현)

  • Min, Kyoung-Wook;Han, Eun-Young;Kim, Gwang-Soo
    • The KIPS Transactions:PartD
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    • v.11D no.6
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    • pp.1247-1258
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    • 2004
  • The LBS(Location-Based Service), which is based on individual's mobility, is required increasingly as mobile telecommunication and various infrastructures have developed rapidly. The technologies for LBS are location determination technology, service platform technology, contents provider technology and moving object database technology generally. Among these, service platform must be interoperable with location gate-way server and provide common function of billing, authentification, protect location information, privacy control, location trigger and intelligent acquisition and so on. The TTA(Telecommunications Technology Association) published specification that defines a standard protocol for safe and simple interface between LBS client and LBS platform and the OpenLS(Open Location Service) in OGC (Open GIS Consortium) released implementation specifications for providing Location based core services. In this paper, we implemented service platform for LBS which is able to interoperable with location gateway server and contents provider and is caracterized as follows. First, it could require and response location information from different types of location gateway server with same interface. Second, it complies with the standard interfaces with OpenLS 4 contents providers for core LBS. Third, it could provide location of wired phone as well as wireless mobile terminal compling with the standard protocol. Last, it could provide trajectorH information based past location as well as current location, because it is able to interoperable with moving object DBMS. This paper contributes to the construction and practical use of LBS by providing the method of implementation of service platform for LBS.

LOTOS Protocol Conformance Testing for Formal Description Specifications (형식 기술 기법에 의한 LOTOS 프로토콜 적합성 시험)

  • Chin, Byoung-Moon;Kim, Sung-Un;Ryu, Young-Suk
    • The Transactions of the Korea Information Processing Society
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    • v.4 no.7
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    • pp.1821-1841
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    • 1997
  • This paper presents an automated protocol conformance test sequence generation based on formal methods for LOTOS specification by using and applying many existing related algorithms and technique, such as the testing framework, Rural Chinese Postman tour concepts. We use the state-transition graphs obtained from LOTOS specifications by means of the CAESAR tool. This tool compiles a specification written in LOTOS into an extended Petri net, from which a transition graph of a event finite-state machine(EvFSM) including data is generated. A new characterizing sequence(CS), called Unique Event sequence(UE sequence) is defined. An UE sequence for a state is a sequence of accepted gate events that is unique for this state. Some experiences about UE sequence, partial UE sequence and signature are also explained. These sequences are combined with the concept of the Rural Chinese Postman Tour to obtain an optimal test sequence which is a minimum cost tour of the reference transition graph of the EvFSM. This paper also presents a fault coverage estimation experience of an automated method for optimized test sequences generation and the translation of the test sequence obtained by using our tool to TTCN notation are also given. A prototype of the proposed framework has been built with special attention to real application in order to generated the executable test cases in an automatic way. This formal method on conformance testing can be applied to the protocols related to IN, PCS and ATM for the purpose of verifying the correctness of implementation with respect to the given specification.

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Impacts on Water Quality to an Artificial Lake Due to Sudden Disturbance of Sediments (급격한 저니토 교란이 인공 하구호 수질에 미치는 영향)

  • 서승원;김정훈
    • Journal of Korean Society of Coastal and Ocean Engineers
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    • v.15 no.1
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    • pp.39-50
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    • 2003
  • This study aims to figure out water quality impacts due to sudden disturbances of sediments during dike construction in land reclamation for the northern part of the Siwhaho Lake where heavily deteriorated settlements from upstream loadings are outstanding. We exploit a 3-D water quality model CE-QUAL-ICM combined with a hydrodynamic model TIDE3D. Simulations are done accounting water-sediment interaction in a 4-$\sigma$ layers. Long-term simulation for 1-year shows that bottom layers around the disturbance location are only affected and marks very high concentration. Complete vertical mixing appears at least 5km apart to downward due to complex effects of geometry, bathymetry and river inflows. It should be addressed that existing condition of the Siwhaho Lake stands for high concentration of COD and TP in winter and spring due to relatively high incoming loadings, however the effect of sediment disturbances yields reverse phenomena, i.e., impacts of dike construction arise greatly in summer and fall. Refined grid system consisting of 150m${\times}$150m rectangular grid, which is doubled system compared to previous study (Suh et al.,2002), gives affordable results by reducing flux differences through a cell especially in front of gate.

Future Inundation Risk Evaluation of Farmland in the Moohan Stream Watershed Based on CMIP5 and CMIP6 GCMs (CMIP5 및 CMIP6 GCM 기반 무한천 유역 농경지 미래 침수 위험도 분석)

  • Jun, Sang Min;Hwang, Soonho;Kim, Jihye;Kwak, Jihye;Kim, Kyeung;Lee, Hyun Ji;Kim, Seokhyeon;Cho, Jaepil;Lee, Jae Nam;Kang, Moon Seong
    • Journal of The Korean Society of Agricultural Engineers
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    • v.62 no.6
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    • pp.131-142
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    • 2020
  • The objective of this study was to evaluate future inundation risk of farmland according to the application of coupled model intercomparison project phase 5 (CMIP5) and coupled model intercomparison project phase 6 (CMIP6). In this study, future weather data based on CMIP5 and CMIP6 general circulation model (GCM) were collected, and inundation was simulated using the river modeling system for small agricultural watershed (RMS) and GATE2018 in the Tanjung district of the Moohan stream watershed. Although the average probable rainfall of CMIP5 and CMIP6 did not show significant differences as a result of calculating the probability rainfall, the difference between the minimum and maximum values was significantly larger in CMIP6. The results of the flood discharge calculation and the inundation risk assessment showed similar to trends to those of probability rainfall calculations. The risk of inundation in the future period was found to increase in all sub-watersheds, and the risk of inundation has been analyzed to increase significantly, especially if CMIP6 data are used. Therefore, it is necessary to consider climate change effects by utilizing CMIP6-based future weather data when designing and reinforcing water structures in agricultural areas in the future. The results of this study are expected to be used as basic data for utilizing CMIP6-based future weather data.

An Analysis on the Title Sequence of Disney Full-length Animation (디즈니 장편애니메이션 타이틀 시퀀스 분석)

  • Kim, Seol-Mi;Kim, Kyu-Jung
    • Cartoon and Animation Studies
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    • s.39
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    • pp.183-214
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    • 2015
  • For a long time, Disney has made animations including world views such as family-focused, conservative ideology, happy ending, etc. for families. Periodical situation and spectators' demands have been changed little by little, but Disney is still a company who is the most successful both nominally and virtually in animation industry. For the secrets of their success, there is fantasy world of fabricated animation, thoroughly organized story and image. When spectators watch animations, their sufficient immersion in the fantasy is to let them forget realities. In the introduction of Disney animations, spectators turn off the switch of realities and turn on the switch of fantasy world through the procedure to recognize and confirm virtual world sufficiently. In the switch of the introduction used frequently by Disney, there are four methods. First is to start while opening the cover of storybook. Second is to start while storyteller gives a talk directly. Third is to start with live action film and continue to animation. Fourth is musical method. Those four switches play a role of the gate which distinguishes spectators' realities from Disney's fantasy clearly. The process makes an opportunity to set spectators who feel uneasy due to the vague boundary between realities and fantasy at ease and let them immerse in animation sufficiently with mind at ease.

Design of PMOS-Diode Type eFuse OTP Memory IP (PMOS-다이오드 형태의 eFuse OTP IP 설계)

  • Kim, Young-Hee;Jin, Hongzhou;Ha, Yoon-Gyu;Ha, Pan-Bong
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.13 no.1
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    • pp.64-71
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    • 2020
  • eFuse OTP memory IP is required to trim the analog circuit of the gate driving chip of the power semiconductor device. Conventional NMOS diode-type eFuse OTP memory cells have a small cell size, but require one more deep N-well (DNW) mask. In this paper, we propose a small PMOS-diode type eFuse OTP memory cell without the need for additional processing in the CMOS process. The proposed PMOS-diode type eFuse OTP memory cell is composed of a PMOS transistor formed in the N-WELL and an eFuse link, which is a memory element and uses a pn junction diode parasitic in the PMOS transistor. A core driving circuit for driving the array of PMOS diode-type eFuse memory cells is proposed, and the SPICE simulation results show that the proposed core circuit can be used to sense post-program resistance of 61㏀. The layout sizes of PMOS-diode type eFuse OTP memory cell and 512b eFuse OTP memory IP designed using 0.13㎛ BCD process are 3.475㎛ × 4.21㎛ (= 14.62975㎛2) and 119.315㎛ × 341.95㎛ (= 0.0408mm2), respectively. After testing at the wafer level, it was confirmed that it was normally programmed.