• Proceedings of the Korean Information Science Society Conference
• /
• 1998.10b
• /
• pp.36-38
• /
• 1998

객체지향 데이터베이스 시스템의 표준 질의어로 사용되는 OQL은 SQL과 달리 select-from-where절 어디서나 중첩 질의를 자유롭게 허용하며, 이러한 중첩 질의는 질의어 수행 성능에 중요한 영향을 미치므로, OQL을 처리하는 질의 처리기에서는 이를 반드시 고려해 주어야 한다. 본 논문은 모노이드 컴프리핸션 해석(monoid comprehension calculus)을 이용하여, OQL 질의 처리기에서 중첩 질의의 중첩 구조를 제거할 수 있도록 해주고, 나아가 기존 질의 처리기에서 중첩질의 처리 기능을 추가하는데 있어, 이미 구현되어 있는 질의 최적화 모듈과 질의 수행 모듈의 수정을 최소화할 수 있는 중첩 질의 구조 제거용 전위 모듈(unnesting front-end)을 설계하고 구현하였다.

• Proceedings of the KSR Conference
• /
• 1998.05a
• /
• pp.361-368
• /
• 1998

Described in this paper is the result of a study on collision analysis of TGV-K using 1-dimensional model for crashworthy design. Crashworthy design of the front end is very important because majority of the impact energy (more than 70%) is absorbed by the crush of the front end when the train is collided with an obstacle like a tank lorry. Guideline for the crashworthy design can be described from the collision analysis of the whole train using a 1-dimensional model. Since the headstock of TGV-K is not designed in a crashworthy point of view, a conceptual design of the headstock to improve crashworthiness is suggested and evaluated using 1-dimensional collision analysis. The suggested design, which adopts an energy absorber and a crashworthy headstock, shows a good behaviour on the accident scenario of SNCF (collision at 110 km/hr against a movable rigid mass of 15 ton).

• Proceedings of the KSR Conference
• /
• 2004.10a
• /
• pp.652-656
• /
• 2004

Crashworthy design of trains is now indispensable procedure in modern railway vehicle design for ensuring the safety of Passengers and crew. It is now widely recognized that a more strategic approach is needed in order to absorb higher level energy in a controlled manner and minimize passenger injuries effectively. The first design step in this strategic approach is the design of the front end structure(so called HE extremities) to absorb a large part of total impact energy and then the structure of passengers non-accommodation zones(so called LE extremities) is designed to absorb the rest of impact energy. In this paper, the passengers entrance door area is selected as the LE(low energy) extremities and the design of the LEE was carried out. The main part of LEE design procedures is the design of energy absorbing tubes. For this purpose, the several tube candidates are introduced and compared to each others with numerical crash simulation.

• The Magazine of the IEIE
• /
• v.30 no.9
• /
• pp.1002-1011
• /
• 2003

In this paper, we introduce an integrated SoC front-end design & verification environment which can be practically used in the embedded 32-bit processor-core SoC VLSI design. Our introduced SoC design & verification environment integrates two most important flows, such as the RTL power estimation and code coverage analysis, with the functional verification (chip validation) flow which is used in the conventional simulation-based design. For this, we developed two simulation-based inhouse tools, RTL power estimator and code coverage analyzer, and used them to adopt them to our RTL design and to increase the design quality of that. Our integrated design environment also includes basic design and verification flows such as the gate-level functional verification with back annotation information and test vector capture & replay environment.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.11 no.4
• /
• pp.256-261
• /
• 2011

We demonstrate 3-Gb/s wireless link using a 60-GHz receiver front-end fabricated in $0.25-{\mu}m$ SiGe:C bipolar complementary metal oxide semiconductor (BiCMOS) and a mixed-mode quadrature phase-shift keying (QPSK) demodulator fabricated in 60-nm CMOS. The 60-GHz receiver consists of a low-noise amplifier and a down-conversion mixer. It has the peak conversion gain of 16 dB at 62 GHz and the 3-dB intermediate-frequency bandwidth of 6 GHz. The demodulator using 1-bit sampling scheme can demodulate up to 4.8-Gb/s QPSK signals. We achieve successful transmission of 3-Gb/s data in 60 GHz through 2-m wireless link.

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.52 no.4
• /
• pp.148-153
• /
• 2003

In this paper, the low voltage 3V Sigma-Delta Digital Analog Converter(DAC) is designed for using in the transmitter of ADSL analog front-end. We have developed the CMOS DAC according to ANSI T1.413-2(DMT) standard specifications of the chip. The designed 4th-order DAC is composed of three block which are 1-bit DAC, 1st-order Switched-Capacitor filter and analog active 2nd-order Resistor-Capacitor(RC) filter. The HSPICE simulation of the designed DAC showing 65db SNR, is connected with 1.1MHz continuous lowpass filter. And also, we have performed the circuits verification and layout verification(ERC, DRC, LVS) followed by fabrication using TSMC 2-poly 5-metal p-substrate CMOS $0.35{\mu}m$ processing parameter. Finally, the chip testing has been performed and presented in the results.

• Journal of international Conference on Electrical Machines and Systems
• /
• v.2 no.2
• /
• pp.197-201
• /
• 2013

Cascaded H-bridge multilevel inverter requires independent DC voltage sources to produce multi output voltage levels. When it needs to generate more levels in the output voltage wave, the number of independent DC voltage sources usually limits its extension. To solve this problem, we propose a cascaded H-bridge multilevel inverter employing a front-end flyback converter for unifying input DC voltage sources. After theoretical analysis of the proposed circuit, we verify the validity of the proposed inverter using computer-aided simulations and experiments.

• Proceedings of the KIPE Conference
• /
• 2017.07a
• /
• pp.435-436
• /
• 2017

This papaer is study on thermal analysis of the active-front-end(AFE) rectifier for solid-state-transformer(SST) applications. finite element analysis simulation model is combined by switching component model, power diode and heat-sink model. thermal model is calculated by computer program and feedback the result. using simulation result analysis switching loss and compare to thermal diffusion of the heat in the model for steady-state operation.

• International Journal of Automotive Technology
• /
• v.6 no.5
• /
• pp.491-499
• /
• 2005

There are different types of vehicle impacts recorded every year, resulting in many injuries and fatalities. The severity of these impacts depends on the aggressivety and incompatibility of vehicle-to-roadside hardware impacts. The aim of this paper is to investigate and to enhance crashworthiness in the case of full barrier impact using a new idea of crash improvement. Two different types of smart structures have been proposed to support the function of the existing vehicle. The work carried out in this paper includes developing and analyzing mathematical models of vehicle-to-barrier impact for the two types of smart structures. It is proven from analytical analysis that the mathematical models can be used in an effective way to give a quick insight of real life crashes. Moreover, it is shown that these models are valid and flexible, and can be useful in optimization studies.

• Proceedings of the KIEE Conference
• /
• 1998.11a
• /
• pp.121-124
• /
• 1998

Front end AC to DC converters of the boost type are used in traction applications for generating the DC link for the inverters. A GTO based converter is usually switched with a switching frequency of 300 to 500Hz, resulting in low frequency harmonic problems. In order to avoid this, multiple converters with Phase shifted carrier waveforms are used to suppress the low frequency harmonics. A detailed study of an AC to DC converter, with two converters parallely operated with Phase shifted carrier wave farms is Presented in this paper.