• Korean Institute of Interior Design Journal
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• v.26 no.4
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• pp.84-92
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• 2017

Just as the front gate is located at the meeting point between the house and the street, the Subject and the Other face each other the same way. This study examines the relationship between House(subject) and Stree (other) at the boundary of the Front Gate-Face. Pursuing the aspects of the changing Front Gate-Face accordingly to the attitude of the Subject facing the Other, this study tries to analyze the possibilities and significance of the hospitality Front Gate-Face with the ethical point of view of Levinas. As architectural instance, results of examining the Front Gate-Face of traditional houses in Korea, China and Japan are as follows. Front Gate-Face of China is characterized by self-centered introversion to interact with the external world (the other). Front Gate-Face of Japan is characterized by a humble submission to the group. Front Gate-Face of Korea shows however more flexible relationship orientations in terms of hospitality, compared to Japan or China. When looking through hospitality factors, accordingly to the above mentioned Korean hospitality characteristics, the possibilities seem not be exclusively bordered inside the conceptual category perimeter suggested by Levinas' concept of hospitality. It is almost impossible for the nowadays ever-strong privacy culture to not allow room for the architectural structure of an absolute hospitality toward others. However, this impossibility not being absolute, still yields a space for a significant possibility to explore.

• Journal of the Korean housing association
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• v.20 no.4
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• pp.1-9
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• 2009

In this study, an examination and an analysis are carried out on the forms and components of the access spaces of hotel entrances from the front gate of five star hotels in Jejudo, Korea. The results of the study are as follows. In terms of the arrangement of the hotel, city hotels with a relatively narrow site area are influenced by site shape, while resort hotels with a relatively wide site area are affected by the environment. However, the location of the front gate was determined by the access road from the outside. Therefore, forms of access space are related to the front gate, which is governed by the access road, and to the entrance, which is determined by the hotel arrangement. If the front gate is in line with the hotel entrance, a straight line and the hotel are arranged vertically to the front gate(side arrangement) or the hotel is arranged horizontally to the front gate, but if the entrance is not in line with the front gate, it appears as a curved shape. However, those who use their own cars have a variety of choices for access route depending on the location of the parking lot.

• Journal of the Architectural Institute of Korea Planning & Design
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• v.35 no.2
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• pp.73-82
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• 2019

The purpose of this study was to analyze the area of the southern gate in ancient temples. As the southern gate played a role of the front gate, the national or royal ceremonies had been held around the southern gates. The ancient southern gate of temples has had the place for the huge ceremonies such as a royal parade and an inspection of troops. Moreover, this place was recorded in the 'Samkooksagi(三國史記)' as Jeon-Ro(前路). The Southern gate and the Jeon-Ro had been planned together in the front area of the ancient temples, and the gate had been designed to look down the Jeon-Ro. These findings can be verified through the result of a recent excavation at a site of Hwangnyongsa temple in Gyeongju. This research confirmed that the huge ceremonies had been held at the Jeon-Ro including the area of southern gates. Furthermore, a Hwangnyongsa temple is regarded as a concrete case of verifying the composition of the area of Southern gate.

• Advances in nano research
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• v.3 no.1
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• pp.49-54
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• 2015

The structure represents symmetrical metal electrode (gate 1) - front $SiO_2$ layer - n-Si nanowire FET - buried $SiO_2$ layer - metal electrode (gate 2). At the symmetrical gate voltages high conductive regions near the gate 1 - front $SiO_2$ and gate 2 - buried $SiO_2$ interfaces correspondingly, and low conductive region in the central region of the NW are formed. Possibilities of applications of nanosize FETs at the deep inversion and depletion as a distributed capacitance are demonstrated. Capacity density is an order to ${\sim}{\mu}F/cm^2$. The charge density, it distribution and capacity value in the nanowire can be controlled by a small changes in the gate voltages. at the non-symmetrical gate voltages high conductive regions will move to corresponding interfaces and low conductive region will modulate non-symmetrically. In this case source-drain current of the FET will redistributed and change current way. This gives opportunity to investigate surface and bulk transport processes in the nanosize inversion channel.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.16-24
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• 2009

Independent-gate-mode double-gate(IGM-DG) MOSFET overcomes the limitation of 3-terminal device structure, and enables to operate with different voltages for front-gate and back-gate. Therefore, circuit designs becomes not only simple, but also area-efficient due to the controllability of the 4th terminal provided by IGM-DG MOSFETs. In this paper, an RF receiver utilizing IGM-DG MOSFETs is presented and also, the circuit performance is verified by the HSPICE simulations. Besides, the circuit analysis and optimization are performed for various IGM-DG characteristics.

• Journal of electromagnetic engineering and science
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• v.8 no.3
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• pp.134-137
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• 2008

This paper proposes a novel quadrature VCO(QVCO) based on direct back-gate second harmonic coupling. The QVCO directly couples the current sources of the conventional LC VCOs through the back-gate instead of front-gate to generate quadrature signals. By the second harmonic injection locking, the two LC VCOs can generate quadrature signals without using on-chip transformer, or stability problem that is inherent in the direct front-gate second harmonic coupling. The proposed QVCO is implemented in $0.18{\mu}m$ CMOS technology operating at 2 GHz with 5.0 mA core current consumption from 1.8 V power supply. The measured phase noise of the proposed QVCO is - 63 dBc/Hz at 10 kHz offset, -95 dBc/Hz at 100 kHz offset, and -116 dBc/Hz at 1 MHz offset from the 2 GHz output frequency, respectively. The calculated figure of merit(FOM) is about -174 dBc/Hz at 1 MHz offset. The measured image band rejection is 46 dB which corresponds to the phase error of $0.6^{\circ}$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.11
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• pp.2621-2626
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• 2013

This paper has presented the potential distribution for asymmetric double gate(DG) MOSFET, and sloved Poisson equation to obtain the analytical solution of potential distribution. The symmetric DGMOSFET where both the front and the back gates are tied together is three terminal device and has the same current controllability for front and back gates. Meanwhile the asymmetric DGMOSFET is four terminal device and can separately determine current controllability for front and back gates. To approximate with experimental values, we have used the Gaussian function as doping distribution in Poisson equation. The potential distribution has been observed for gate bias voltage and gate oxide thickness and channel doping concentration of the asymmetric DGMOSFET. As a results, we know potential distribution is greatly changed for gate bias voltage and gate oxide thickness, especially for gate to increase gate oxide thickness. Also the potential distribution for source is changed greater than one of drain with increasing of channel doping concentration.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.691-694
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• 2013

This paper has presented the potential distribution for asymmetric double gate(DG) MOSFET, and sloved Poisson equation to obtain the analytical solution of potential distribution. The symmetric DGMOSFET where both the front and the back gates are tied together is three terminal device and has the same current controllability for front and back gates. Meanwhile the asymmetric DGMOSFET is four terminal device and can separately determine current controllability for front and back gates. To approximate with experimental values, we have used the Gaussian function as charge distribution in Poisson equation. The potential distribution has been observed for gate bias voltage and gate oxide thickness and channel doping concentration of the asymmetric DGMOSFET. As a results, we know potential distribution is greatly changed for gate bias voltage and gate oxide thickness, especially for gate to increase gate oxide thickness. Also the potential distribution for source is changed greater than one of drain with increasing of channel doping concentration.

• Journal of architectural history
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• v.18 no.5
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• pp.81-100
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• 2009

The study on Buddhism architecture in early Joseon dynasty was inactive. The period of King Sejo is important for studying the trend of Buddhism architecture in early Joseon, that was transmitted from the end of Goryeo dynasty, but it was difficult to know its exact situation due to lack of related records. The records were all written by Kim Su-ohn, which are Wongaksabi' 'Sangwonsajungchanggi' 'Bongseonsagi 'Geonginsajungchanggi'. The main hall was mainly second floor and there were necessarily annexed buildings at the right and left of the main hall. So the plane figure of $\Box\Box\Box$ was shown. It was a main stream for main hall. This layout may be referred to search for the origin of the layout in courtyard based structure(中庭形) in the late Joseon dynasty. Most of temples had 3 gates. Some part of horizontal corridor was used as 2 gates and the outer gate, far from main hall, was without corridor. The gate leading to front yard of main hall was called front gate, the next middle gate and the outer gate was Oisamun(外沙門) or Samun(沙門). Im most of the temples, people could enter into the front yard through pavilion which had the function of bell tower. The pavilions were located between front gate and first corridor. It is thought that this layout of the place for making bean curd outside the temple area will contribute to different studies on temples making bean cure in the future. The records about temples's foundation studied above are a little different between temples, but have more similarities. There common denominators represent the architecture tendency of Buddhist temples in the related period. It is thought that such a tendency was also shown on architecture of other temples during the reign of King Sejo as well as Buddhist temples.

• Journal of information and communication convergence engineering
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• v.8 no.1
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• pp.107-111
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• 2010

This paper has presented the dependence of the threshold voltage on back gate bias and drain voltage for FinFET. The FinFET has three gates such as the front gate, side and back gate. Threshold voltage is defined as the front gate bias when drain current is 1 micro ampere as the onset of the turn-on condition. In this paper threshold voltage is investigated into the analytical potential model derived from three dimensional Poisson's equation with the variation of the back gate bias and drain voltage. The threshold voltage of a transistor is one of the key parameters in the design of CMOS circuits. The threshold voltage, which described the degree of short channel effects, has been extensively investigated. As known from the down scaling rules, the threshold voltage has been presented in the case that drain voltage is the 1.0V above, which is set as the maximum supply voltage, and the drain induced barrier lowing(DIBL), drain bias dependent threshold voltage, is obtained using this model.