• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.155-158
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• 2005

An invesitigation on power consumption of a mobile multimedia system using OFDM and MDVS technique is reported here. Analysis and simulation are performed to find the significances of proposed Microscopic Dynamic Voltage Scaling(MDVS) tehnique[4] on digital processor in terms of power saving. A study is also made to show power reduction in mobile multimedia system by incorporating OFDM modulation scheme in RF front-end. Finally, overall power consumption by functionally distinguished blocks ie. RF front-end, digital processor and human interface unit is shown here. Total power consumption is 8.2W for 2Mbps SD-quality WCDMA multimedia video service - the power consumption of digital processor is 3.9W(48%), the power consumption of RF front-end is 3.2W (36%), and the power consumption of interface is 1.8W(16%). Power saving of applying purposed MDVS technique is 35% in digital processor, and power saving of OFDM technique is 10-12dB in RF front-end.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.1
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• pp.11-20
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• 2000

Many object query languages including OQL(the query language proposed by theOBMG) allow query block to be nested in any clause: select clause, from clause and where clause. The processing of nested queries can affect the performance of its query processor Therefore, an OQL query processor should have effective optimizing techniques for nested queries. This paper designs and implements a new framework of an unnesting front-end for an OQL query processor This unnesting module can minimize implementation overhead when developing a new OQL processor or extending an existing query processor to be equipped with an unnesting facility This is accomplished by separation between logical algebra operators used in an unnesting front-end and ones in a query optimizer.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.391-394
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• 2006

The paper deals with the experimental GNSS receiver built at the Czech Technical University for experiments with the real GNSS signal. The receiver is based on software defined radio architecture. Receiver consists of the RF front end and a digital processor based on programmable logic. Receiver RF front end supports GPS L1, L2, L5, WAAS/EGNOS, GALILEO L1, E5A, E5B signals as well as GLONASS L1 and L2 signals. The digital processor is based on Field Programmable Gate Array (FPGA) which supports embedded processor. The receiver is used for various experiments with the GNSS signals like GPS L1/EGNOS receiver, GLONASS receiver and investigation of the EGNOS signal availability for a land mobile user. On the base of experimental GNSS receiver the GPS L1, L2, EGNOS receiver for railway application was designed. The experimental receiver is also used in GNSS monitoring station, which is independent monitoring facility providing also raw monitoring data of the GPS, EGNOS and Galileo systems via internet.

• Journal of Power Electronics
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• v.16 no.1
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• pp.190-204
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• 2016

An active front end (AFE) is required for a three-phase induction motor (IM) fed by a voltage source inverter (VSI), because of the increasing need to derive quality current from the utility end without sacrificing the power factor (PF). This study investigates a proportional-plus-integral (PI) controller based AFE topology that uses a super-lift converter (SLC). The significance of the proposed SLC, which converts rectified AC supply to geometrically proceed ripple-free DC supply, is explained. Variations in several power quality parameters in the intended IM drive for 0% and 100% loading conditions are demonstrated. A simulation is conducted by using MATLAB/Simulink software, and a prototype is built with a field programmable gate array (FPGA) Spartan-6 processor. Simulation results are correlated with the experimental results obtained from a 0.5 HP IM drive prototype with speed feedback and a voltage/frequency (V/f) control strategy. The proposed AFE topology using SLC is suitable for three-phase IM drives, considering the supply end PF, the DC-link voltage and current, the total harmonic distortion (THD) in supply current, and the speed response of IM.

• The Magazine of the IEIE
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• v.30 no.9
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• pp.1002-1011
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• 2003

In this paper, we introduce an integrated SoC front-end design & verification environment which can be practically used in the embedded 32-bit processor-core SoC VLSI design. Our introduced SoC design & verification environment integrates two most important flows, such as the RTL power estimation and code coverage analysis, with the functional verification (chip validation) flow which is used in the conventional simulation-based design. For this, we developed two simulation-based inhouse tools, RTL power estimator and code coverage analyzer, and used them to adopt them to our RTL design and to increase the design quality of that. Our integrated design environment also includes basic design and verification flows such as the gate-level functional verification with back annotation information and test vector capture & replay environment.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.186-194
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• 1996

The SliM (sliding memory plane) array processor has been proposed to alleviate disadvantages of existing mesh-connected SIMD(single instruction stream- multiple data streams) array processors, such as the inter-PE(processing element) communication overhead, the data I/O overhead and complicated interconnections. This paper presents the deisgn and implementation of SliM image processor ASIC (application specific integrated circuit) chip consisting of mesh connected 5 X 5 PE. The PE architecture implemented here is quite different from the originally proposed PE. We have performed the front-end design, such as VHDL (VHSIC hardware description language)modeling, logic synthesis and simulation, and have doen the back-end design procedure. The SliM ASIC chip used the VTI 0.8$\mu$m standard cell library (v8r4.4) has 55,255 gates and twenty-five 128 X 9 bit SRAM modules. The chip has the 326.71 X 313.24mil$^{2}$ die size and is packed using the 144 pin MQFP. The chip operates perfectly at 25 MHz and gives 625 MIPS. For performance evaluation, we developed parallel algorithms and the performance results showed improvement compared with existing image processors.

• The Transactions of the Korea Information Processing Society
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• v.4 no.1
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• pp.255-269
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• 1997

In this paper, we describe the implementation of C cross-compiler for the ES-C2340 DSP2 processor by using the GNU compiler. For the rapid and efficient developing of the compiler and other parts like the processor-dependent back -end which is implemented newly to build the compiler. This approach has several advantages. First, as we use GNU compiler's well-proved excellent optimization method and multi-language support capability, we can improve he efficiency and generality of the compiler. Second, as we concentrate on the high-level language as logic approving tool in processor developing process. And to support the cross-compiler, we also implement a text-level pre-linker.

• Journal of Biomedical Engineering Research
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• v.16 no.1
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• pp.101-106
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• 1995

In this paper, the patient monitor consisting of ECG/Respiration Amplification, Front end CPU, Main CPU, Main Controller, Video Amplifier, Display Controller, Waveform Generator, Bus & Power Supply, 8097 Processor was developed. This patient monitor measures the patient's states in the hospital such as elecctro-cardiography, respiration, blood pressurae and temperature. The control and processing methods based on micro-processor employ the flexibility, extensibility over other conventional system. The followings are incorporated in this system. First, ECG/RESP measures the respiration by impedence pneumography. Second, FECPU utilizes an Intel 8031 microcontroller. Third, Controller function originate from a LSI CRT controller.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.2
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• pp.138-148
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• 1988

In this paper, it is focused on the design of the FEP system that executes the access control programs instead of the hos processor. And so the FEP system improves the network flexibility and redues the installation costs of network. The design criterion of the FEP system is based on the ISDN construction which presents the information channel in thr future information society. The proposed hardwares and transmission softwares use the basic transmission rate of 64Kbps, and the contents of file service throuth this FEP system are listed by FTAM services.

• Journal of Energy Engineering
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• v.18 no.3
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• pp.147-155
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• 2009

Demand for distributed source by new and renewable energy has been gradually increasing recently. For the characteristics of distributed generation, distributed source is located near the distribution system and customers' buildings and can be operated in standalone mode or in interface mode with distribution system. When the distributed sources are interfaced with distribution system, the standard for interfacing distributed source with existing distribution system and operation manual should be updated with revisions in order to manage the distributed source effectively and operate the distribution system stably because how to operate the interfaced system is different from that of existing distribution system. In this paper, the FEP(Front End Processor) using the international standard protocol IEC-60870 for interfacing with distributed resources was designed. The designed system was verified via the test result using main control system for distributed generation and RTU(Remote Terminal Unit) for interface with distributed power generating.