• Journal of Power Electronics
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• 제18권5호
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• pp.1523-1535
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• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• 전자공학회논문지
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• 제50권10호
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• pp.76-81
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• 2013

130nm CMOS 공정 라이브러리를 이용하여 125MHz로 동작하는 새로운 위상 주파수 검출기 기반 DPLL을 설계하였다. 이 DPLL은 중간 주파수대 응용을 위해 지터와 록 시간을 줄이려고 전형적인 DPLL에 반전 에지 검출기를 포함하고 있다. XOR 기반 반전 에지 검출기들은 출력을 보다 빨리 변화시키기 위하여 기준 신호보다 빠른 전이를 얻는데 사용된다. HSPICE 시뮬 레이터는 모의실험을 위해 Cadence환경에서 사용되었다. 제안된 위상 주파수 검출기를 가진 DPLL의 성능은 종래의 위상 주 파수 검출기를 가진 것의 성능과 비교하였다. 종래의 PLL은 약 0.1245 ns의 최대 지터를 가지고 록 하는데 최소 $2.144{\mu}s$가 걸린 반면에, 제안한 검출기를 가진 PLL은 약 0.1142 ns의 최대 지터를 가지고 록 하는데 $0.304{\mu}s$가 걸린다.

• 한국통신학회논문지
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• 제24권8A호
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• pp.1252-1258
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• 1999

본 논문에서는 10-MHz 대역폭을 갖는 무선가입자망용 중간주파수 아날로그 IC 설계에 관하여 논한다. 본 IC는 RF 부와 MODEM사이에서 인터페이스 역할을 하며, 수신 단에서는 중간주파수 신호를 기저대역으로 저역변환을 하고 송신 단에서는 기저대역 신호를 중간주파수 신호로 바꾸어 준다. 본 회로는 이득조절증폭기, 위상잠금회로, 저역통과필터, 아날로그-디지털 및 디지털-아날로그 변환기로 구성된다. 위상잠금회로에서 전압발진기 및 분주기, 위상비교기, 전하펌핑회로는 동일 칩 안에 구현하였고, 외부소자로는 루프필터용 소자와 LC 탱크 소자만이 사용되었다. 본 IC는 0.6-$\mu\textrm{m}$ CMOS 공정에 의하여 제작되었고, 전체 크기는 4 mm $\times$ 4 mm 이며, 3.3 V에서 약 57mA를 소모하였다.

• Journal of Communications and Networks
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• 제8권1호
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• pp.8-12
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• 2006

Master-slave (M-S) strategies implemented with chain circuits are the main option in order to distribute clock signals along synchronous networks in several telecommunication and control applications. Here, we study the two types of masterslave chains: Without clock feedback, i.e., one-way master-slave (OWMS) and with clock feedback, i.e., two-way master-slave (TWMS) considering the slave nodes as second-order phase-locked loops (PLL) for several types of loop low-pass filters.

• 한국정보전자통신기술학회논문지
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• 제12권1호
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• pp.1-6
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• 2019

본 논문에서는 복수개의 부궤환 루프를 도입하여 칩 크기를 획기적으로 줄이면서 잡음 특성을 유지할 수 있는 위상고정루프를 제안하였다. 칩 면적을 최소화하는 것이 주목표이므로 하나의 작은 크기의 커패시터로 구성된 1차 루프필터와 복수개의 FVC를 사용하여 위상고정루프를 설계하였다. 전압제어 발진기에 연결된 복수개의 주파수-전압 변환 회로(frequency voltage converter : FVC)는 위상고정루프 내부에 복수개의 부궤환 루프를 만든다. 제안된 위상고정루프에서는 복수개의 부궤환 루프가 크기가 아주 작은 하나의 커패시터로만 구성된 루프필터를 가진 위상고정루프를 안정하게 동작하도록 해준다. 제안된 위상고정루프는 1.8V $0.18{\mu}m$ CMOS 공정을 이용하여 설계되었다. 시뮬레이션 결과는 1.6ps 지터와 $10{\mu}s$ 위상고장시간을 보여주었다.

• Journal of Power Electronics
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• 제18권5호
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• pp.1347-1356
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• 2018

In a three-phase system, three-phase AC signals can be translated into two-phase DC signals through a coordinate transformation. Thus, the PI regulator can realize a zero steady-state error for the DC signals. In the control of a three-phase grid-connected inverter, the phase angle of grid is normally detected by a phase-locked loop (PLL) and takes part in a coordinate transformation. A novel control strategy for a three-phase grid-connected inverter with a frequency-locked loop (FLL) based on coordinate transformation is proposed in this paper. The inverter is controlled as a current supply. The grid angle, which takes part in the coordinate transformation, is replaced by a periodic linear changing angle from $-{\pi}$ to ${\pi}$. The changing angle has the same frequency but a different phase than the grid angle. The frequency of the changing angle tracks the grid frequency by the negative feedback of the reactive power, which forms a FLL. The control strategy applies to non-ideal grids and it is a lot simpler than the control strategies with a PLL that are applied to non-ideal grids. The structure of the FLL is established. The principle and advantages of the proposed control strategy are discussed. The theoretical analysis is confirmed by experimental results.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.1097-1100
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• 1998

In this paper, the PLL(Phase-Locked Loops) for low voltage and high speed operation is described. In other to obtaining above objects, new CMOS circuit technologies have been used in the each block circuit of PLL. It operates with a lock range from 110 up to 700 MHz and has a peak to peak jitter of 50 ps at operating frequency of 250 MHz. It was fabricated in a $0.6\mu\textrm{m}$ CMOS technology and dissipated 45 mW from a single 3.3V.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1233-1236
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• 2003

This paper proposes a phase-locked loop (PLL) that achieves one-cycle lock acquisition by employing the lock-acquisition circuit (LAC). The LAC produces the initial analog voltage ( v$_{c}$ ) that corresponds to the input frequency. When the transfer curve of the LAC matches that of the voltage-controlled oscillator (VCO), one-cycle locking can be possible. By HSPICE simulations, the proposed LAC is proved to be applicable to any kinds of PLL [1][2][3].].

• Journal of Electrical Engineering and Technology
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• 제9권2호
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• pp.771-776
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• 2014

In this paper, an agile programmable chirp spread spectrum generator for wideband frequency-jamming applications from 20 MHz to 3 GHz is proposed. A frequency-mixing architecture using two voltage-controlled oscillators is used to achieve a wideband operating frequency range, and the direct digital synthesizer (DDS)-based chirping method with a two-point modulation technique is employed to provide a programmable and consistent chirp bandwidth. The proposed signal generator provides the various programmable FM signals from 20 MHz to 3 GHz with a modulation bandwidth from 0 to 400 MHz. The prototype successfully demonstrates arbitrary sequential jamming operation with a fast band-to-band hopping time of < 10 ${\mu}sec$.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2017년도 추계학술대회
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• pp.63-64
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• 2017

This paper proposes a speed estimator for sensorless control of diesel-generator (genset) systems, where the speed of the genset is calculated from the back-EMF frequency of the generator. The back-EMF frequency is extracted from a phase output current by using multiple second-order generalized integrators (SOGIs) connected in parallel and series and separated frequency-locked loops. The proposed method (PS-SOGI-FLL) is able to estimate the fundamental frequency in the distorted output current with high accuracy and strong robustness. Simulation results are shown to verify the validity of the proposed method.