• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.7
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• pp.23-29
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• 2012

The LC-based digitally controlled oscillator (LC-DCO), a key component of the all digital phase locked loop (ADPLL), is designed using $0.18{\mu}m$ RFCMOS process with 1.8 V supply. The NMOS core with double cross-coupled pair is chosen to realize wide tuning range, and the PMOS varactor pair that has small capacitance of a few aF and the capacitive degeneration technique to shrink the capacitive element are adopted to obtain the high frequency resolution. Also, the noise filtering technique is used to improve phase noise performance. Measurement results show the center frequency of 2.7 GHz, the tuning range of 2.5 GHz and the high frequency resolution of 2.9 kHz ~7.1 kHz. Also the fine tuning range and the current consumption of the core could be controlled by using the array of PMOS transistors using current biasing. The current consumption is between 17 mA and 26 mA at 1.8V supply voltage. The proposed DCO could be used widely in various communication system.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.163-166
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• 1999

In this paper, frequency synthesizer that can be used in IMT-2000 was designed and fabricated using dual loop PLL(Phase Locked Loop). For improving phase noise characteristic Voltage Controlled Oscillator was fabricated using coaxial resonator and eliminated frequency divider using SPD as phase detector and increased open loop gain. Fabricated frequency synthesizer had 1.82㎓ center frequency, 160MHz tuning range and -119.73㏈c/Hz low phase noise characteristic.

• Journal of information and communication convergence engineering
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• v.15 no.1
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• pp.1-6
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• 2017

In this study, we develop and experimentally evaluate an ultra-wideband (UWB) slot antenna with a polygon tuning stub. The proposed antenna consists of a polygon slot with a $50-{\Omega}$ feed line. The effects of various parameters of the polygon-shaped slot and the polygon tuning stub on UWB applications are investigated. The optimum parameters were obtained using the Ansys HFSS software. The results of the studies on the surface current distributions of the operating frequency bands were discussed. The proposed antenna is fabricated on an inexpensive FR-4 substrate with the overall dimensions of $28.0mm{\times}30.0mm$. The measured results confirm that the proposed antenna covers frequencies from 2.58 GHz to 13.27 GHz, which is the UWB frequency range. Further, the proposed UWB antenna also exhibited that omni-directionality in the H-plane gain varied from 1.185 to 7.246 dBi. The good antenna characteristics of the proposed antenna make it suitable for UWB system applications.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.34 no.5
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• pp.637-644
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• 2010

A vibration-powered piezoelectric energy harvester yields the maximum power output when its resonant frequency is made equal to the excitation frequency; however, the power output is dramatically decreased when the energy harvester is operated at off-resonance frequency. It has been observed that the resonant frequency of a piezoelectric energy harvester may change with time and that the excitation frequency often varies when the energy harvester is used in real applications. Hence, in this study, we propose a piezoelectric energy-harvesting module that is suitable for excitations in a certain frequency range. The frequency characteristics of the electrical output of the module are studied through analysis and experiment. A simple frequency tuning method is also suggested for the proposed energy-harvesting module; in this method, frequency tuning is achieved by changing the electrical connections between the constituent energy-harvesting units of the module.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.501-503
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• 2008

This paper presents the design of a 2.4 GHz low phase noise fully integrated LC Voltage-Controlled-Oscillator (VCO) in $0.18{\mu}m$ CMOS technology. The VCO is without any tail bias current sources for a low phase noise and, in which differential varactors are adopted for the symmetry of the circuit. At the same time, the use of differential varactors pairs reduces the tuning range, i.e., the frequency range versus VTUNE, so that the phase noise becomes lower. The simulation results show the achieved phase noise of -138.5 dBc/Hz at 3 MHz offset, while the VCO core draws 3.9mA of current from a 1.8V supply. The tuning range is from 2.28GHz to 2.55 GHz.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2004.04a
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• pp.251-258
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• 2004

This paper presents the parameter study of multiple tuned liquid damper (MTLCD) applied to the 76-story benchmark building. A parameter study involves the effects of number of TLCD, frequency range, and central tuning frequency ratio, which are important parameters of MTLCD. The performance of MTLCD is carried out numerical analysis which reflects the nonlinear property of liquid motion. The parameters of TLCD exist different each optimal values according to mass ratio. The performance of single-TLCD (STLCD) is sensitive for tuning frequency ratio. Therefore, MTLCD is proposed to protect such the shortcoming of STLCD. The result of numerical analysis presents improved performance for robustness of MTLCD

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.73-78
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• 2011

A frequency synthesizer for DAB applications is designed using $0.18{\mu}m$ CMOS process with 1.8V supply. NP-core type is chosen for VCO core to improve low power characteristic and symmetric characteristic of output waveform. VCO range is 1302.34 MHz - 1949.51 MHz using switchable capacitor bank and varactor bank. Varactor biases that improve varactor capacitance characteristics were minimized as two, $K_{vco}$(VCO gain) is maintained using technique of varactor bank switching. Intervals of $K_{vco}$ are maintained adding VCO frequency compensation logic. Each block of VCO and frequency synthesizer designed $0.18{\mu}m$ CMOS process with 1.8V supply is verified by Cadence Spectre, measured VCO consumes 9mA current, and is 39.8% tuning range, total power consumption of the frequency synthesizer is 18mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.117-124
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• 2009

This paper describes a 3 to 5 GHz frequency synthesizer for MB-OFDM (Multi-Band OFDM) UWB (Ultra- Wideband) application using 0.13 ${\mu}m$ CMOS process. The frequency synthesizer operates in the band group 1 whose center frequencies are 3432 MHz 3960 MHz, and 4488 MHz. To cover the overall frequencies of group 1, an efficient frequency planning minimizing a number of blocks and the power consumption are proposed. And, a high-frequency VCO and LO Mixer architecture are also presented in this paper. A new mixed coarse tuning scheme that utilizes the MIM capacitance, the varactor arrays, and the DAC is proposed to expand the VCO tuning range. The frequency synthesizer can also provide the clock for the ADC in baseband modem. So, the PLL for the ADC in the baseband modem can be removed with this frequency synthesizer. The single PLL and two SSB-mixers consume 60 mW from a 1.2 sV supply. The VCO tuning range is 1.2 GHz. The simulated phase noise of the VCO is -112 dBc/Hz at 1 MHz offset. The die area is 2 ${\times}$ 2mm$^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.94-99
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• 2010

This paper presents a design procedure of digitally controlled oscillator(DCO) for power optimization. By controlling coarse tuning bits and fine tuning bits of DCO, the proposed design procedure can optimize the power dissipation and does not affect the LSB resolution, frequency range, linearity, portability. For optimization, the relationship between control bits and power dissipation of the DCO was analyzed. The DCO circuits using and unusing proposed design technique have been designed, simulated and proved using 0.13um, 1.2V CMOS library. The DCO circuit with proposed design technique has operation range between 283MHz and 1.1GHz and has 1.7ps LSB resolution and consumes 2.789mW at frequency of 1GHz.

• Journal of the Korean Society of Laryngology, Phoniatrics and Logopedics
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• v.16 no.1
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• pp.10-14
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• 2005

Background and Objectives : Vowels are characterized on the basis of formant patterns. The first formant(F1) is determined by high-low placement of the tongue, and the second formant (F2) by front-back placement of the tongue. The fundamental frequency(F0) of a soprano often exceed the normal frequency of the first formant. And the vocal intensity is boosted when F0 is high and a harmonic coincides with a formant. This is called a formant tuning. Experienced singers thus learned how to tune their formants over a resonable range by lowering the tongue to maximize their vocal intensity. So, the current study aimed to identify the formant tuning in one experienced soprano by comparing the first formants of vowel [i] in three different voice production : speech, ascending scale, and vocalize. Materials and Method : All voices recordings of vowel [i] in speech, ascending scale (from F4 note to A4 note), and vocalize(:Ridente la calam") were made with digital audio tape-corder in a sound treated room. And the captured data were analyzed by the long term average(LTA) power spectrum using the FFT algorithm of the Computerized Speech Lab(CSL, Kay elementrics, Model, 4300B). Results : Although the first formant of vowel [i] in speech was 238Hz, those of ascending scale [i] were 377Hz, 405Hz, 453Hz respectively in F4(349z), G4(392Hz), A4(440Hz) note, and 722Hz, 820Hz, 918Hz respectively in F5 (698Hz), G5(784Hz), A5(880Hz) note. In vocalize, first formants of [i] were 380Hz, 398Hz, 453Hz respectively in F4, G4, A4 note, and 720Hz, 821Hz, 890Hz respectively in F5, G5, A5 note. Conclusion : These results showed that the first formant of ascending scale and vocalize sustained higher frequency than fundamental frequency in high pitch. This finding implicates that the formant tuning of vowel [i] in ascending scale was also noted in vocalize.