• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.85-91
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• 2009

Recently, the LCD has high market share in TV market. The use of motion images in portable devices like DMB, PMP and Cell Phone is growing rapidly. One of the technique of enhancing the LCD's characteristic which is the slow response time. But, the technique requires a lot of memory usage, because of the requirement of frame memory. In this paper, we propose a reduction method for the frame memory that is required for LCD overdrive. Proposed overdrive architecture based on modified DWT-Inverse DWT and Color Conversion. The proposed architecture has a considerable PSNR. At once, it uses 50% of frame memory size and reduces 15% of frame memory size compare with previous architecture. The design was implemented using Xilinx Vertex4 and had 2172 Slice except Memory.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.997-998
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• 2008

In this paper, we proposed a reduced memory overdrive architecture. Proposed overdrive architecture consists of 2D-DWT filter, BLI and Color Conversion block. For Frame Memory reduction we eliminated HH data in DWT-IDWT process and converted color space RGB into YCbCr. Consequently, we reduced Frame Memory about 50%.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.258-262
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• 2009

In this paper, we propose an effective memory reduction algorithm to reduce the amount of reference frame buffer and memory bandwidth in video encoder and decoder. In general video codecs, decoded previous frames should be stored and referred to reduce temporal redundancy. Recently, reference frames are recompressed for memory efficiency and bandwidth reduction between a main processor and external memory. However, these algorithms could hurt coding efficiency. Several algorithms have been proposed to reduce the amount of reference memory with minimum quality degradation. They still suffer from quality degradation with fixed-bit allocation. In this paper, we propose an adaptive block-based min-max quantization that considers local characteristics of image. In the proposed algorithm, basic process unit is $8{\times}8$ for memory alignment and apply an adaptive quantization to each $4{\times}4$ block for minimizing quality degradation. We found that the proposed algorithm could improve approximately 37.5% in coding efficiency, compared with an existing memory reduction algorithm, at the same memory reduction rate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.37-42
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• 2008

In H.264/AVC decoder, intra predictor, motion compensator, and deblocking filter need to read reference images in external frame memory in decoding process. They read external frame memory very frequently, which lowers system operation speed and increases power consumption. This paper proposes a intra predictor integrated with motion compensator without external frame memory. It achieves power reduction and memory bandwidth minimization by exploiting data reuse of common and repetitive pixels. The proposed infra predictor achieves more than $45%\;{\sim}\;75%$ cycle time reduction compared with conventional intra predictors.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.933-936
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• 2005

Applications of LCD panel are getting more increased for motion-image applications. However, when the motion-images are displayed on LCD panels, they may be blurred due to slow response time of liquid crystal (LC). One of the solutions of the problem is overdrive technique. The technique has a lot of memory usage. In this paper, we propose a reduction method of the frame memory that is required for LCD overdrive. Proposed overdrive architecture consists of line-based lifting integer (5, 3) DWT filter for image data reduction and BLI (Bi-Linearly Interpolation) LUT for pixel value accelerating.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.6B
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• pp.1183-1190
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• 1999

This paper presents an efficient hardware architecture to improve the frame memory interface occupying the largest hardware area together with motion estimator in implementing MPEG-2 video encoder as an ASIC chip. In this architecture, the memory size for internal data buffering and hardware area for frame memory interface control logic are reduced through the efficient memory map organization of the external SDRAM having dual bank and memory access timing optimization between the video encoder and external SDRAM. In this design, 0.5 m, CMOS, TLM (Triple Layer Metal) standard cells are used as design libraries and VHDL simulator and logic synthesis tools are used for hardware design add verification. The hardware emulator modeled by C-language is exploited for various test vector generation and functional verification. The architecture of the improved frame memory interface occupies about 58% less hardware area than the existing architecture[2-3], and it results in the total hardware area reduction up to 24.3%. Thus, the (act that the frame memory interface influences on the whole area of the video encoder severely is presented as a result.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.32-35
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• 2002

The work focuses on the development of a Cu lead-frame with a single-sided adhesive tape for cost reduction and reliability improvement of LOC (lead on chip) package products, which are widely used for the plastic-encapsulation of memory chips. Most of memory chips are assembled by the LOC packaging process where the top surface of the chip is directly attached to the area of the lead-frame with a double-sided adhesive tape. However, since the lower adhesive layer of the double-sided adhesive tape reveals the disparity in the coefficient of thermal expansion from the silicon chip by more than 20 times, it often causes thermal displacement-induced damage of the IC pattern on the active chip surface during the reliability test. So, in order to solve these problems, in the resent work, the double-sided adhesive tape is replaced by a single-sided adhesive tape. The single-sided adhesive tape does net include the lower adhesive layer but instead, uses adhesive materials, which are filled in clear holes of the base film, just for the attachment of the lead-frame to the top surface of the memory chip. Since thermal expansion of the adhesive materials can be accommodated by the base film, memory product packaged using the lead-flame with the single-sided adhesive tape is shown to have much improved reliability. Author allied this invention to the Korea Patent Office for a patent (4-2000-00097-9).

• Smart Structures and Systems
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• v.31 no.5
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• pp.531-543
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• 2023

Base isolation is one of the most widely implemented and well-known technique to reduce structural vibration and damages during an earthquake. However, while the base-isolated structure reduces storey drift significantly, it also increases the base drifts causing many practical problems. This study proposes the use of Shape Memory Alloys (SMA) wires for the reduction in base drift while controlling the overall structure vibrations. A multi-degree-of-freedom (MDOF) structure along with base isolators and Shape-Memory-Alloys (SMA) wires in diagonal is tested experimentally and analytically. The isolation bearing considered in this study consists of laminates of steel and silicon rubber. The performance of the proposed structure is evaluated and studied under different loadings including harmonic loading and seismic excitation. To assess the seismic performance of the proposed structure, shake table tests are conducted on base-isolated MDOF frame structure incorporating SMA wires, which is subjected to incremental harmonic and historic seismic loadings. Root mean square acceleration, displacement and drift are analyzed and discussed in detail for each story. To better understand the structure response, the percentage reduction of displacement is also determined for each story. The result shows that the reduction in the response of the proposed structure is much better than conventional base-isolated structure.

• Smart Structures and Systems
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• v.25 no.3
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• pp.311-322
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• 2020

This paper studies the influence of parameters of a novel SMA helical spring energy dissipation brace on the seismic resistance of a frame structure. The force-displacement relationship of the SMA springs is established mathematically based on a multilinear constitutive model of the SMA material. Four SMA helical springs are fabricated, and the force-displacement relationship curves of the SMA springs are obtained via tension tests. A numerical dynamic model of a two-floor frame with spring energy dissipation braces is constructed and evaluated via vibration table tests. Then, two spring parameters, namely, the ratio of the helical spring diameter to the wire diameter and the pre-stretch length, are selected to investigate their influences on the seismic responses of the frame structure. The simulation results demonstrate that the optimal ratio of the helical spring diameter to the wire diameter can be found to minimize the absolute acceleration and the relative displacement of the frame structure. Meanwhile, if the pre-stretch length is assigned a suitable value, excellent vibration reduction performance can be realized. Compared with the frame structure without braces, the frames with spring braces exhibit highly satisfactory seismic resistance performance under various earthquake waves. However, it is necessary to select an SMA spring with optimal parameters for realizing optimal vibration reduction performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12B
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• pp.2424-2429
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• 1999

In this paper, we present a memory efficient implementation method of channel encoder using convolutional encoding and interleaving. In conventional method, two separate RAMs must be used for the channel encoder: one RAM for storing frame data and another RAM for interleaving. In our method, without using interleaving RAM, we only use two small RAMs for buffering input frame data. We can process convolutional encoding and interleaving concurrently by using the two RAMs. There are several advantages when applying channel encoder designed using this method to several digital mobile telecommunications : the reduction of memory size ranging 33 % - 60 %, simplified procedure of receiving frame data, and resultant timing margin gained by the simplified procedure.