• Title/Summary/Keyword: Fowler-Nordheim tunnel

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The microstructure and conduction mechanism of the nonlinear ZnO varistor with $Al_2O_3$ additions ($Al_2O_3$가 미량 첨가된 비선형성 ZnO 바리스터의 미세구조와 전도기구)

  • 한세원;강형부;김형식
    • Electrical & Electronic Materials
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    • v.9 no.7
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    • pp.708-718
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    • 1996
  • The microstructure and electrical properties of the nonlinear ZnO varistor with A1$_{2}$ $O_{3}$ additions is investigated. The variation of nonlinear behavior with A1$_{2}$ $O_{3}$ additions is indicated from J-E and C-V measurement to be a result of the change of the interface defects density $N_{t}$ at the grain boundaries and the donor concentration $N_{d}$ in the ZnO grains. The optimum composition which has the nonlinear coefficients of -57 was observed in the sample with 0.005wt% A1$_{2}$ $O_{3}$ additions. The conduction mechanism at the pre-breakdown region is consistent with a Schottky thermal emission process obeying a relation given by $J^{\var}$exp[-(.psi.-.betha. $E^{1}$2/)kT] and the conduction process at the breakdown region follows a Fowler-Nordheim tunneling mechanism of the form $J^{\var}$exp(-.gamma./E).

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Tunnel Barrier Engineering for Non-Volatile Memory

  • Jung, Jong-Wan;Cho, Won-Ju
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.1
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    • pp.32-39
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    • 2008
  • Tunnel oxide of non-volatile memory (NVM) devices would be very difficult to downscale if ten-year data retention were still needed. This requirement limits further improvement of device performance in terms of programming speed and operating voltages. Consequently, for low-power applications with Fowler-Nordheim programming such as NAND, program and erase voltages are essentially sustained at unacceptably high levels. A promising solution for tunnel oxide scaling is tunnel barrier engineering (TBE), which uses multiple dielectric stacks to enhance field-sensitivity. This allows for shorter writing/erasing times and/or lower operating voltages than single $SiO_2$ tunnel oxide without altering the ten-year data retention constraint. In this paper, two approaches for tunnel barrier engineering are compared: the crested barrier and variable oxide thickness. Key results of TBE and its applications for NVM are also addressed.

The NAND Type Flash EEPROM using the Scaled SCNOSFET (Scaled SONOSFET를 이용한 NAND형 Flash EEPROM)

  • Kim, Ju-Yeon;Kim, Byeong-Cheol;Kim, Seon-Ju;Seo, Gwang-Yeol
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.49 no.1
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    • pp.1-7
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    • 2000
  • The SNOSFET memory devices with ultrathin ONO(tunnel oxide-nitride-blocking oxide) gate dielectric were fabricated using n-well CMOS process and investigated its characteristics. The thicknesses of tunnel oxide, nitride and blocking oxide were $23{\AA},\; 53{\AA}\; and\; 33{\AA}$, respectively. Auger analysis shows that the ONO layer is made up of $SiO_2(upper layer of blocking oxide)/O-rich\; SiO_x\N\_y$. It clearly shows that the converting layer with $SiO_x\N\_y(lower layer of blocking oxide)/N-rich SiO_x\N\_y(nitride)/O-rich SiO_x\N\_y(tunnel oxide)$. It clearly shows that the converting layer with $SiO_x\N\_y$ phase exists near the interface between the blocking oxide and nitride. The programming condition of +8 V, 20 ms, -8 V, 50 ms is determined and data retention over 10 years is obtained. Under the condition of 8 V programming, it was confirmed that the modified Fowler-Nordheim tunneling id dominant charge transport mechanism. The programmed threshold voltage is distributed less than 0.1 V so that the reading error of memory stated can be minimized. An $8\times8$ NAND type flash EEPROM with SONOSFET memory cell was designed and simulated with the extracted SPICE parameters. The sufficient read cell current was obtained and the upper limit of $V_{TH}$ for write state was over 2V.

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Design of a 512b Multi-Time Programmable Memory IPs for PMICs (PMIC용 512비트 MTP 메모리 IP설계)

  • Jang, Ji-Hye;Ha, Pan-Bong;Kim, Young-Hee
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.9 no.1
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    • pp.120-131
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    • 2016
  • In this paper, a 512b MTP memory IP is designed by using MTP memory cells which are written by the FN (Fowler-Nordheim) tunneling method with only MV (medium voltage) devices of 5V which uses the back-gate bias, that is VNN (negative voltage). The used MTP cell consists of a CG (control gate) capacitor, a TG (tunnel gate) transistor, and a select transistor. To reduce the size of the MTP memory cell, just two PWs (P-wells) are used: one for the TG and the select transistors; and the other for the CG capacitor. In addition, just one DNW (deep N-well) is used for the entire 512b memory cell array. VPP and VNN generators supplying pumping voltages of ${\pm}8V$ which are insensitive to PVT variations since VPP and VNN level detectors are designed by a regulated voltage, V1V (=1V), provided by a BGR voltage generator.

Fabrication of engineered tunnel-barrier memory with $SiO_2/HfO_2/Al_2O_3$ tunnel layer ($SiO_2/HfO_2/Al_2O_3$ 적층구조 터널링 절연막을 적용한 차세대 비휘발성 메모리의 제작)

  • Oh, Se-Man;Park, Gun-Ho;Kim, Kwan-Su;Jung, Jong-Wan;Jeong, Hong-Bae;Cho, Won-Ju
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.06a
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    • pp.129-130
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    • 2009
  • The P/E characteristics of $HfO_2$ CTF memory capacitor with $SiO_2/HfO_2/Al_2O_3$(OHA) engineered tunnel barrier were investigated. After a growth of thermal oxide with a thickness of 2 nm, 1 nm $HfO_2$ and 3 $Al_2O_3$ layers were deposited by atomic layer deposition (ALD) system. The band offset was calculated by analysis of conduction mechanisms through Fowler-Nordheim (FN) plot and Direct Tunneling (DT) plot. Moreover the PIE characteristics of $HfO_2$ CTF memory capacitor with OHA tunnel barrier was presented.

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Magnetic Tunnel Junctions with AlN and AlO Barriers

  • Yoon, Tae-Sick;Yoshimura, Satoru;Tsunoda, Masakiyo;Takahashi, Migaku;Park, Bum-Chan;Lee, Young-Woo;Li, Ying;Kim, Chong-Oh
    • Journal of Magnetics
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    • v.9 no.1
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    • pp.17-22
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    • 2004
  • We studied the magnetotransport properties of tunnel junctions with AlO and AlN barriers fabricated using microwave-excited plasma. The plasma nitridation process provided wider controllability than the plasma oxidization for the formation of MTJs with ultra-thin insulating layer, because of the slow nitriding rate of metal Al layers, comparing with the oxidizing rate of them. High tunnel magnetoresistance (TMR) ratios of 49 and 44% with respective resistance-area product $(R{\times}A) of 3 {\times} 10^4 and 6 {\times} 10^3 {\Omega}{\mu}m^2$ were obtained in the Co-Fe/Al-N/Co-Fe MTJs. We conclude that AlN is a hopeful barrier material to realize MTJs with high TMR ratio and low $R{\times}A$ for high performance MRAM cells. In addition, in order to clarify the annealing temperature dependence of TMR, the local transport properties were measured for Ta $50{\AA} /Cu 200 {\AA}/Ta 50 {\AA}/Ni_{76}Fe_{24} 20 {\AA}/Cu 50 {\AA}/Mn_{75}Ir_{25} 100 {\AA}/Co_{71}Fe_{29} 40 {\AA}/Al-O$ junction with $d_{Al}= 8 {\AA} and P_{O2}{\times}t_{0X}/ = 8.4 {\times} 10^4$ at various temperatures. The current histogram statistically calculated from the electrical current image was well in accord with the fitting result considering the Gaussian distribution and Fowler-Nordheim equation. After annealing at $340^{\circ}C$, where the TMR ratio of the corresponding MTJ had the maximum value of 44%, the average barrier height increased to 1.12 eV and its standard deviation decreased to 0.1 eV. The increase of TMR ratio after annealing could be well explained by the enhancement of the average barrier height and the reduction of its fluctuation.

Study on the Fabrication of Tunnel Type $E^2PROM$ and Its Characteristics (터널링형 $E^2PROM$ 제작 및 그 특성에 관한 연구)

  • Kim, Jong Dae;Kim, Sung Ihl;Kim, Bo Woo;Lee, Jin Hyo
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.23 no.1
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    • pp.65-73
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    • 1986
  • Experiment have been conducted about thin oxide characteristics according to O2/N2 ratio needed for EEPROM cell fabrication. As a result, we think that there is no problem even if we grow oxide layer with large O2/N2 ratio and short exidation time and when the water is implated by As before oxidation, the oxide breakdown field is about IMV/cm lower than that is not implanted. Especially, the thin oxide characteristic seems to be affected largely by wafer cleaning and oxidation in air. On the basis of these, tunnel type EEPROM cell is fabricated by 3um CMOS process and its characteristic is studied. Tunnel oxide thickness(100\ulcorner is chosen to allow Fowler-Nordheim tunneling to charge the floating gate at the desired programming voltage and tunnel area(2x2um\ulcorneris chosen to increase capacitive coupling ratio. For program operation, high voltage (20-22V) is applied to the control gate, while both drain and source are gdrounded. The drain voltage for erase is 16V. It is shown that charge retention characteristics is not limited by leakage in the oxide and program/erase endurance is over 10E4 cycles of program erase operation.

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Electrical characteristic of insulator in tunnel-harrier memory using high-k (High-k를 이용한 터널베리어 메모리의 절연막 특성 평가)

  • Oh, Se-Man;Jung, Myung-Ho;Park, Gun-Ho;Kim, Kwan-Su;Jo, Young-Hun;Jung, Jong-Wan;Jung, Hong-Bea;Cho, Won-Ju
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.11a
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    • pp.262-263
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    • 2008
  • The Metal-Insulator-Silicon (MIS) capacitors with $SiO_2$ and high-k dielectric were investigated. The high-k dielectrics were obtained by atomic layer deposit (ALD) system. The electrical characteristics were investigated by measuring the current-voltage (I-V) characteristics. The conduction mechanisms were analyzed by using the Fowler-Nordheim (FN) plot and Direct Tunneling (DT) plot. As a result, the MIS capacitors with high-k dielectrics have lower leakage current densities than conventional tunnel-barrier with $SiO_2$ dielectrics.

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Tunneling Properties in High-k Insulators with Engineered Tunnel Barrier for Nonvolatile Memory (차세대 비휘발성 메모리에 사용되는 High-k 절연막의 터널링 특성)

  • Oh, Se-Man;Jung, Myung-Ho;Park, Gun-Ho;Kim, Kwan-Su;Chung, Hong-Bay;Lee, Young-Hie;Cho, Won-Ju
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.22 no.6
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    • pp.466-468
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    • 2009
  • The metal-insulator-silicon (MIS) capacitors with $SiO_2$ and high-k dielectrics ($HfO_2$, $Al_2O_3$) were fabricated, and the current-voltage characteristics were investigated. Especially, an effective barrier height between metal gate and dielectric was extracted by using Fowler-Nordheim (FN) plot and Direct Tunneling (DT) plot of quantum mechanical(QM) modeling. The calculated barrier heights of thermal $SiO_2$, ALD $SiO_2$, $HfO_2$ and $Al_2O_3$ are 3.35 eV, 0.6 eV, 1.75 eV, and 2.65 eV, respectively. Therefore, the performance of non-volatile memory devices can be improved by using engineered tunnel barrier which is considered effective barrier height of high-k materials.

A New Programming Method of Scaled SONOS Flash Memory Ensuring 1$\times$10$^{6}$ Program/Erase Cycles and Beyond (1x10$^{6}$ 회 이상의 프로그램/소거 반복을 보장하는 Scaled SONOS 플래시메모리의 새로운 프로그래밍 방법)

  • 김병철;안호명;이상배;한태현;서광열
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.07a
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    • pp.54-57
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    • 2002
  • In this study, a new programming method, to minimize the generation of Si-SiO$_2$ interface traps of scaled SONOS flash memory as a function of number of program/erase cycles has been proposed. In the proposed programming method, power supply voltage is applied to the gate, forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim (MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and drain are open. A single power supply operation of 3 V and a high endurance of 1${\times}$10$\^$6/ prograss/erase cycles can be realized by the proposed programming method. The asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics of scaled SONOS devices because electrical stress applied to the Si-SiO$_2$ interface is reduced by short programming time.

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