• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.500-504
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• 1997

Current source inverter drives of auto sequentially commutated type are very popular in high power applications, because of simple power circuit configuration with four quadrant operation. But the six-step current output create harmonic problems and the input power factor of such a drive is not always good. In this respect pulse width modulated drives using gate turn off thyristors ( GTO ) are finding application, especially in traction drives. However the switching and snubber loses of a GTO do not permit the inverter switching frequency go beyond a few hundred hertz.This will again introduce low frequency harmonic problems. Multi level inverters of the 3-level and 5-level can be considered as an alternative to overcome the low switching frequency harmonic problem of the 2-level GTO inverters. But with multi level inverters the complexity of the power circuit increases. In this paper a combination of multi level ( 2-level and 3-level ) inverters and multi phase induction motor ( 3-phase and 6-phase) configurations are presented for high power VSI drives for traction applications with reduced inverter switching frequency requirements coupled with reduced voltage rating for the power switch.

• Journal of IKEEE
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• v.26 no.1
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• pp.95-103
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• 2022

In this paper, the efficiency of a sensorless method with square-wave injection for a low-cost inverter, so called B4 inverter is presented. This inverter comprises only 4 switches to reduce system cost. It is distinguished from the conventional B6 inverter that has 6 of switching elements. The B4 inverter, injected a 1 kHz of harmonic wave, has been modelled using the functions and library in Matlab/Simulink. This paper described each component of sensorless algorithm. Among them, the Notch Filter is used to extract the harmonic component of the phase current and a second-order low-pass filter was used to reduce the ripple of the estimated speed. It is shown through simulation that the rotor angle of a permanent magnet synchronous motor is detected by multiplying the current waveform extracted using the notch filter by the harmonic voltage. The feasibility of the proposed method is shown through Simulink simulation.

• Journal of Power Electronics
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• v.13 no.4
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• pp.719-728
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• 2013

A novel hybrid active power filter (NHAPF) that can be adopted in high-voltage systems is proposed in this paper. The topological structure and filtering principle of the compensating system is provided and analyzed, respectively. Different controlling strategies are also presented to select the suitable strategy for the compensation system. Based on the selected strategy, the harmonic suppression function is used to analyze the influence of system parameters on the compensating system with MATLAB. Moreover, parameters in the injection branch are designed and analyzed. The performance of the proposed NHAPF in harmonic suppression and reactive power compensation is simulated with PSim. Thereafter, the overall control method is proposed. Simulation analysis and real experiments show that the proposed NHAPF exhibits good harmonic suppression and reactive power compensation. The proposed compensated system is based on the three-phase four-switch inverter, which is inexpensive, and the control method is verified for validity and effectiveness.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.152-162
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• 2003

In this paper, Binary to Quaternary Converter(BQC), Quaternary to Binary Converter(QBC) and Quaternary inverter circuit, which is the basic logic gate, have been proposed based on voltage mode. The BQC converts the two bit input binary signals to one digit quaternary output signal. The QBC converts the one digit quaternary input signal to two bit binary output signals. And two circuits consist of Down-literal circuit(DLC) and combinational logic block(CLC). In the implementation of quaternary inverter circuit, DLC is used for reference voltage generation and control signal, only switch part is implemented with conventional MOS transistors. The proposed circuits are simulated in 0.35 ${\mu}{\textrm}{m}$ N-well doubly-poly four-metal CMOS technology with a single +3V supply voltage. Simulation results of these circuit show 250MHz sampling rate, 0.6mW power consumption and maintain output voltage level in 0.1V.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.2
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• pp.88-95
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• 2008

This paper proposes a fast fault detection algorithm under open-circuit fault of a switch for a brushless DC(BLDC) motor drive system. This proposed method is configured without the additional devices for fault detection and identification. The fault detection and identification are achieved by a simple algorithm using the operating characteristic of the BLDC motor. After the fault identification, the drive system is reconfigured for continuous operation. This system is reconfigured by four-switch topology connecting a faulty leg to the middle point of DC-link bidirectional switches. This proposed method can also be embedded into existing BLDC motor drive systems as a subroutine without excessive computational effort. The feasibility of a the proposed fault detection algorithm is validated in simulation and experiment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.38-44
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• 2007

This paper describes a 12 bit 80MHz CMOS D/A converter for wireless transceiver. Proposed circuit in the paper employes segmented structure which consists of four stage 3bit thermometer decoders. Proposed D/A converter is manufactured 0.35um CMOS n-well digital standard process and measurement results show a ${\pm}1.36SB/{\pm}0.62LSB$ of INL/DNL and $46pV{\cdot}s$ of glitch energy. SNR and SFDR are measured to be 58.5dB and 64.97dB @ Fs=80MHz and Fin=19MHz with a total power consumption of 99mW. Such results proved that our work has low power consumption, high linearity, low glitch and improved dynamic performance. Therefore, our work can be appled to various high speed and high performance circuits.