• ETRI Journal
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• v.29 no.3
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• pp.408-410
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• 2007

A 9-bit 80-MS/s CMOS pipelined folding analog-to-digital converter employing offset-canceled preamplifiers and a subranging scheme is proposed to extend the resolution of a folding architecture. A fully differential dc-decoupled structure achieves high linearity in circuit design. The measured differential nonlinearity and integral nonlinearity of the prototype are ${\pm}0.6$ LSB and ${\pm}1.6$ LSB, respectively.

• Proceedings of the KSME Conference
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• 2001.06c
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• pp.100-105
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• 2001

The manufacturing of metal bellows consists of the four main forming processes, deep-drawing, ironing, tube bulging and folding. Among these, the bulging and folding processes are critically important because the quality of metal bellows is greatly influenced by the forming conditions of these processes. In the present study, the finite element analysis technique is applied to the bulging and folding processes to obtain information about the design parameters of a metal bellows.

• Journal of the Chungcheong Mathematical Society
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• v.18 no.1
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• pp.65-72
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• 2005

In this paper we will introduce all types of the isotwist foldings of a manifold M into itself. The limits of the isotwist foldings of a manifold are obtained. Also the relations between conditional retraction and this type of the folding are achieved. Finally the variant and invariant of the immersion under the type of folding are deduced.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.986-989
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• 1999

An 12bit current-mode folding and interpolation analog to digital converter (ADC) with multiplied folding amplifiers is proposed in this paper. A current - mode multiplied folding amplifier is employed not only to reduced the number of reference current source, but also to decrease a power dissipation within the ADC. The designed ADC fabricated by a 0.6${\mu}{\textrm}{m}$ n-well CMOS double metal/single poly process. The simulation result shows the power dissipation of 280㎽ with a power supply of 5V.

• Journal of the Chungcheong Mathematical Society
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• v.18 no.2
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• pp.145-159
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• 2005

In this paper we introduced the concept of perfect folding defined on $E^2$ which equipped by perfect k-coloring of r-monohedral tillings. Then we studied the different cases of perfect foldings of 4-monohedral and 3-monohedral tillings of $E^2$. Also the permutations describe each folding are obtained.

• Applied Biological Chemistry
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• v.47 no.1
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• pp.33-40
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• 2004

Thermodynamic properties of ubiquitin transient folding intermediate were studied by measuring folding kinetics in varying temperatures and denaturant concentrations. Through quantitative kinetic modeling, the equilibrium constant, hence folding free energy, between unfolded state and intermediate state in several different temperatures were calculated. Using these values, the thermodynamic parameters were estimated. The heat capacity change $({\Delta}C_p)$ upon formation of folding intermediate from unfolded state were estimated to be around 80% of the overall folding reaction, indicating that ubiquitin folding intermediate is highly compact. At room temperature, the changes of enthalpy and entropy upon formation of the intermediate state were observed to be positive. The positive enthalpy change suggests that the breaking up of the highly ordered solvent structure surrounding hydrophobic side-chain upon formation of intermediate state. This positive enthalpy was compensated for by the positive entropy change of whole system so that formation of transient intermediate has negative free energy.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.198-204
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• 2001

In this paper, a 3V 8-bit 200MSPS CMOS folding / interpolation A/D Converter is proposed. It employs an efficient architecture whose FR(Folding Rate) is 8, NFB(Number of Folding Block) is 4, and IR (Interpolating Rate) is 8. For the purpose of improved SNDR by to be low input frequency, distributed track and hold circuits are included. In order to obtain a high speed and low power operation, further, a novel dynamic latch and digital encoder based on a novel delay error correction are proposed. The chip has been fabricated with a 0.35${\mu}{\textrm}{m}$ 2-poly 3-metal n-well CMOS technology. The effective chip area is 1070${\mu}{\textrm}{m}$$\times$650${\mu}{\textrm}{m}$ and it dissipates about 230mW at 3.3V power supply. The INL is within $\pm$1LSB and DNL is within $\pm$1LSB, respectively. The SNDR is about 43㏈, when the input frequency is 10MHz at 200MHz clock frequency.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.11a
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• pp.327-328
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• 2008

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.626-628
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• 2004

This paper describes an 8-bit CMOS folding A/D converter for set-top box. Modular low-power, high-speed CMOS A/D converter for embedded systems aims at design techniques for low-power, high-speed A/D converter processed by the standard CMOS technology. The time-interleaved A/D converter or flash A/D converter are not suitable for the low-power applications. The two-step or multi-step flash A/D converters need a high-speed SHA, which represents a tough task in high-speed analog circuit design. On the other hand, the folding A/D converter is suitable for the low-power, high-speed applications(Embedded system). The simulation results illustrate a conversion rate of 40MSamples/s and a Power dissipation of 80mW(only analog block) at 2.5V supply voltage.

• Journal of the Korean Society for Precision Engineering
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• v.28 no.7
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• pp.821-826
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• 2011

This paper deals with an analysis of dynamic mechanism for the industrial two-step folding automatic door. A nonlinear equation of motion was derived in terms of folding angle to estimate driving forces. Based on this dynamic behavior, time taken during the door's opening well as their velocities were controlled so that the operating conditions can be obtained for the purpose of design. The stiffness of twisting spring was also investigated when the automatic door closed, because a dangerous accident takes place from the door's free falling. The current research will be a very useful tool in the near future for the dynamic analysis for the multi-step folding automatic door.