• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.15 no.1
• /
• pp.264-284
• /
• 2021

As the next-generation network architecture, software-defined networking (SDN) has great potential. But how to forward data packets safely is a big challenge today. In SDN, packets are transferred according to flow rules which are made and delivered by the controller. Once flow rules are modified, the packets might be redirected or dropped. According to related research, we believe that the key to forward data flows safely is keeping the consistency of flow rules. However, existing solutions place little emphasis on the safety of flow rules. After summarizing the shortcomings of the existing solutions, we propose FRChain to ensure the security of SDN data forwarding. FRChain is a novel scheme that uses blockchain to secure flow rules in SDN and to detect compromised nodes in the network when the proportion of malicious nodes is less than one-third. The scheme places the flow strategies into blockchain in form of transactions. Once an unmatched flow rule is detected, the system will issue the problem by initiating a vote and possible attacks will be deduced based on the results. To simulate the scheme, we utilize BigchainDB, which has good performance in data processing, to handle transactions. The experimental results show that the scheme is feasible, and the additional overhead for network performance and system performance is less than similar solutions. Overall, FRChain can detect suspicious behaviors and deduce malicious nodes to keep the consistency of flow rules in SDN.

• Journal of the Korea Society for Simulation
• /
• v.8 no.3
• /
• pp.49-66
• /
• 1999

Semiconductor wafer fabrication is known to be one of the most complex manufacturing processes due to process intricacy, random yields, product diversity, and rapid changing technologies. In this study we are concerned with the impact of lot release and dispatching policies on the performance of semiconductor wafer fabrication facilities. We consider several semiconductor wafer fabrication environments according to the machine failure types such as no failure, normal MTBF, bottleneck with low MTBF, high randomness, and high MTBF cases. Lot release rules to be considered are Deterministic, Poisson process, WR(Workload Regulation), SA(Starvation Avoidance), and Multi-SA. These rules are combined with several dispatching rules such as FIFO (First In First Out), SRPT (Shortest Remaining Processing Time), and NING/M(smallest Number In Next Queue per Machine). We applied the combined policies to each of semiconductor wafer fabrication environments. These policies are assessed in terms of throughput and flow time. Basically Weins fabrication setup was used to make the simulation models. The simulation parameters were obtained through the preliminary simulation experiments. The key results throughout the simulation experiments is that Multi-SA and SA are the most robust rules, which give mostly good performance for any wafer fabrication environments when used with any dispatching rules. The more important result is that for each of wafer fabrication environments there exist the best and worst choices of lot release and dispatching policies. For example, the Poisson release rule results in the least throughput and largest flow time without regard to failure types and dispatching rules.

• 전기의세계
• /
• v.17 no.2
• /
• pp.11-15
• /
• 1968

One of the most important methods used in the modern analysis of linear networks and systems is the signal flow graph technique, first introduced by S.J. Mason in 1953. In essence, the signal-flow graph technique is a graphical method of solving a set of simultaneous. It can, therefore, be regarded as an alternative to the substitution method or the conventional matrix method. Since a flow-graph is the pictorial representation of a set of equations, it has an obvious advantage, i.e., it describes the flow of signals from one point of a system to another. Thus it provides cause-and-effect relationship between signals. And it often significantly reduces the work involved, and also yields an easy, systematic manipulation of variables of interest. Mason's formula is very powerful, but it is applicable only when the desired quantity is the transmission gain between the source node and sink node. In this paper, author summarizes the signal-flow graph technique, and stipulates three rules for conversion of an arbitrary nonsource node into a source node. Then heuses the conversion rules to obtain various quantities, i.e., networks gains, functions and parameters, through simple graphical manipulations.

• Journal of Korean Society of Industrial and Systems Engineering
• /
• v.41 no.2
• /
• pp.47-55
• /
• 2018

The Korean Ministry of Education (MOE) required cash flow statements, instead of fund statements, as a component of the financial statements of the Industry-Academic Cooperation Foundations (IACF) when it revised IACF accounting rules in 2012. While the fund statements were aligned its accounts to the operating statements' accounts level, the newly adopted cash flow statements' accounts retreated to two levels higher than those of the operating statements. It may be resulted from the consideration that IACFs' burden of preparing cash flow statements especially in direct method. To help IACFs prepare the cash flow statements, MOE's guidance on IACF accounting rules introduced cash flow statement preparation method and presented a practical example, but it did not check whether the accounts of the cash flow statement were reconciled to the accounts of corresponding balance sheet and operating statement. That means that the guidance still lacks how to assure it was accurately prepared. Our study proposed cash flow statement preparation using reconciliation method which reconciles cash flow statement accounts' amounts to balance sheet and operating statement accounts' amounts with integrity checking and also provided a practical example by using the same case in MOE's guidance on IACF accounting rules to help IACF accounting personnel to prepare a cash flow statement efficiently.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.11 no.6
• /
• pp.2870-2888
• /
• 2017

Recent studies have shown that the flow table size of hardware SDN switch cannot match the number of concurrent flows. Combined SDN Forwarding Element (CFE), which comprises several software switches and a hardware switch, becomes an alternative approach to tackle this problem. Due to the limited capacity of software switch, the way to route concurrent flows in CFE can largely affect the maximum delay that a flow suffers at CFE. As delay-guarantee is a nontrivial task for network providers with the increasing number of delay-sensitive applications, we propose an analytical model of CFE to evaluate a rules placement solution first. Next, we formulate the problem of Rules Placement with delay guarantee in CFE (RPCFE), and present the genetic-based rules placement (GARP) algorithm to solve the RPCFE problem. Further, we validate the analytical model of CFE through simulations in NS-3 and compare the performance of GARP with three benchmark algorithms.

• Electronics and Telecommunications Trends
• /
• v.37 no.5
• /
• pp.1-10
• /
• 2022

Digital trade rules are crucial in supporting the digital economy as the rules effectively reduce unnecessary trade barriers. This study introduces various approaches that major countries take regarding digital trade policies and rules. Comprehensive and Progressive Agreement for Trans-Pacific Partnership has introduced comprehensive rules on e-commerce, including binding articles on the free flow of information, location of computing facilities, and source code. More recent e-commerce provisions or digital trade agreements cover wider range of issues, from cyber security, artificial intelligence, and data innovation to electronic invoicing and payments. Multilateral negotiations on digital trade rules, including the World Trade Organization E-commerce Joint Statement Initiatives and Indo-Pacific Economic Framework, are in progress. Thus, countries involved are expected to respond to new digital trade issues with long-term strategies considering domestic policy objectives.

• IE interfaces
• /
• v.12 no.3
• /
• pp.437-447
• /
• 1999

Modeling and system development for the fabrication process in the semiconductor manufacturing is presented in this paper. Maximization of wafer production can be achieved by the wafer flow balance under high utilization of bottleneck machines. Relatively simpler model is developed for the fabrication line by considering main characteristics of logistics. Simulation system is developed to evaluate the line performance such as balance rate, utilization, WIP amount and wafer production. Scheduling rules and input rules are suggested, and tested on the simulation system. We have shown that there exists good combination of scheduling and input rules.

• Electronics and Telecommunications Trends
• /
• v.38 no.4
• /
• pp.1-11
• /
• 2023

Trade rules in service and digital sectors mainly focus on reducing regulatory uncertainties by improving transparency and minimizing unnecessary requirements. Recognizing the importance of digital trade rules and trade in information and communication technology (ICT) sectors, governments worldwide have rapidly adopted and expanded rules on free flow of data, personal data protection, electronic authentication, and cybersecurity. On the other hand, advances in technology have led governments to face multiple threats related to cybersecurity, intellectual property (including that related to source code and algorithms), and unauthorized access to proprietary information of their suppliers. This study presents digital trade rules related to digital security emphasizing cybersecurity, source code, and ICT products that use cryptography in different trade agreements. Additionally, it introduces various approaches that major countries are taking to both address digital security issues and seek balance between security enhancement and trade liberalization.

• Journal of Korean Society of Industrial and Systems Engineering
• /
• v.24 no.64
• /
• pp.63-76
• /
• 2001

This paper presents a job-shop type flexible manufacturing system(FMS) scheduling problem and examines the effects of scheduling rules on the performance of FMS. Several machine and AGV scheduling rules are tested against the mean flow-time criterion. In this paper, I compare the rules under various experimental conditions by using an FMS simulation model. One of the objectives of this study is to discuss how the simulation-based scheduling problem can be operated. The other is to measure sensitivity of the rules to changes at inter arrival time, queue capacity, breakdown rates for machines and AGV, and AGV speed. Therefore, the results of simulation experiments were considered on FMS design and operating stages. A comprehensive bibliograph? is also presented in the paper.

• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.39 no.9
• /
• pp.1006-1016
• /
• 1990

A scheduler for a class of Factory Automation (FA) systems is suggested. The technique of Timed Petri Nets is used to model FA systems and, a new concept called Unit Timed Petri Nets is proposed to schedule the system. The scheduler consists of two parts, scheduling rules and input jobs. Since flexibility should be an indispensable ingredient of the scheduler for FA systems, the method using Timed Petri Nets is adopted to represent scheduling rules in a simple and systematic manner and the scheduler is implemented with the PROLOG language. The proposed scheduler is applied to the realistic problem of flow shop.