• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.2
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• pp.428-431
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• 2007

A floating-point number system is used to represent a wide range of real numbers using finite number of bits. The standard the IEEE adopted in 1987 divides the range of real numbers into intervals of [$2^E,2^{E+1}$), where E is an Integer represented with finite bits, and defines equally spaced equal counts of discrete numbers in each interval. Since the numbers are defined discretely, not only the number representation itself includes errors but in floating-point arithmetic some strange behaviors are observed which cannot be agreed with the real world arithmetic. In this paper errors with floating-point number representation, those with arithmetic operations, and those due to order of arithmetic operations are analyzed theoretically with help of and verification with the results of some MATLAB program executions.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.2
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• pp.1-5
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• 2002

Floating point unit system follows IEEE 754 Standard. In this paper, we used 1's complement system instead of 2's complement to practice the arithmetic. By converting we enable this system to compute simply and fast. To improve the speed of newly design adder, we used a transformation Carry selector adder of 53 bits. In paper, a design of floating point unit high efficiency micro processor system about for high speed. 

• IEMEK Journal of Embedded Systems and Applications
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• v.4 no.1
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• pp.1-8
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• 2009

This paper proposes a 24-bit floating point multiply and accumulate(MAC) unit that can be used in geometry transformation process in 3D graphics. The MAC unit is composed of floating point multiplier and floating point accumulator. When separate multiplier and accumulator are used, matrix calculation, used in the transformation process, can't use continuous accumulation values. In the proposed MAC unit the accumulator can get continuous input from the multiplier and the calculation time is reduced. The MAC unit uses about 4,300 gates and can be operated at 150 MHz frequency.

• The Transactions of the Korea Information Processing Society
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• v.4 no.11
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• pp.2861-2873
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• 1997

An FPU(Floating Point unit) is the principle component in high performance computer and is placed on a chip together with main processing unit recently. As a Processing speed of the FPU is accelerated, the rounding stage, which occupies one of the floating point Processing steps for floating point operations, has a considerable effect on overall floating point operations. In this paper, by studying and analyzing the processing flows of the conventional floating point adder/subtractor, multipler and divider, which are main component of the FPU, efficient rounding mechanisms are presented. Proposed mechanisms do not require any additional execution time and any high speed adder for rounding operation. Thus, performance improvement and cost-effective design can be achieved by this approach.

• Journal of Information Processing Systems
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• v.13 no.3
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• pp.573-589
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• 2017

Cloud computing is an attractive solution that can provide low cost storage and powerful processing capabilities for government agencies or enterprises of small and medium size. Yet the confidentiality of information should be considered by any organization migrating to cloud, which makes the research on relational database system based on encryption schemes to preserve the integrity and confidentiality of data in cloud be an interesting subject. So far there have been various solutions for realizing SQL queries on encrypted data in cloud without decryption in advance, where generally homomorphic encryption algorithm is applied to support queries with aggregate functions or numerical computation. But the existing homomorphic encryption algorithms cannot encrypt floating-point numbers. So in this paper, we present a mechanism to enable the trusted party to encrypt the floating-points by homomorphic encryption algorithm and partial trusty server to perform summation on their ciphertexts without revealing the data itself. In the first step, we encode floating-point numbers to hide the decimal points and the positive or negative signs. Then, the codes of floating-point numbers are encrypted by homomorphic encryption algorithm and stored as sequences in cloud. Finally, we use the data structure of DoubleListTree to implement the aggregate function of SUM and later do some extra processes to accomplish the summation.

• The Journal of the Korea institute of electronic communication sciences
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• v.19 no.2
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• pp.409-416
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• 2024

With the expansion of floating-point operation requirements for fast high-speed data signal processing and logic operations, the speed of the floating-point operation unit is the key to affect system operation. This paper studies the performance characteristics of different floating-point multiplier schemes, completes partial product compression in the form of carry and sum, and then uses a carry look-ahead adder to obtain the result. Intel Quartus II CAD tool is used for describing Verilog HDL and evaluating performance results of the floating point multipliers. Floating point multipliers are analyzed and compared based on area, speed, and power consumption. The FMAX of modified Booth encoding with Wallace tree is 33.96 Mhz, which is 2.04 times faster than the booth encoding, 1.62 times faster than the modified booth encoding, 1.04 times faster than the booth encoding with wallace tree. Furthermore, compared to modified booth encoding, the area of modified booth encoding with wallace tree is reduced by 24.88%, and power consumption of that is reduced by 2.5%.

• The KIPS Transactions:PartA
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• v.13A no.3 s.100
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• pp.185-190
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• 2006

JPEG 2000 is used as an alternative to solve the blocking artifact problem with the existing still image compression JPEG algorithm. However, it has shortcomings such as longer floating point computation time and more complexity in the procedure of enhancing the image compression rate and decompression rate. To compensate for these we implemented with hardware the JPEG 2000 algorithm's filter part which requires a lot of floating point computation. This DWT Filter[1] chip is designed on the basis of Daubechies 9/7 filter[6] and is composed of 3-stage pipeline system to optimize the performance and chip size. Our implemented Filter was 7 times faster than software based Filter in the floating point computation.

• Journal of IKEEE
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• v.26 no.2
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• pp.240-248
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• 2022

Floating-point images that express pixel information as real numbers are used in HDR images. There have been various researches on efficient median filter algorithms, but most of them are applicable to 8-bit depth images and there are only a few number of algorithms applicable to floating-point images, including Gil and Werman's algorithm. In this paper, we propose a median filter algorithm that works efficiently on floating-point images by improving Kim's algorithm, which improved Gil and Werman's algorithm. Experimental results show that the execution time is improved by about 10% compared to the Kim's algorithm by reducing the redundant work for the repetitively used binary search tree and applying the inverted index.

• IEMEK Journal of Embedded Systems and Applications
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• v.3 no.4
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• pp.251-259
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• 2008

This paper presents the hardware design of a 32bit floating point based processor. The processor can perform nonlinear functions such as sinusoidal functions, exponential functions, and other mathematical functions. Using the Taylor series and Newton - Raphson method, nonlinear functions are approximated. The processor is actually embedded on an FPGA chip and tested. The numerical accuracy of the functions is compared with those computed by the MATLAB and confirmed the performance of the processor.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1017-1020
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• 1998

We propose an algorithm which processes the floating-point $n_{addition}$traction and rounding in parallel. It also processes multiplication and rounding in the same way. The hardware model is presented that minimizes the delay time to get results for all the rounding modes defined in the IEEE Standards. An unified method to get the three bits(L, G, S)for the rounding is described. We also propose an unified guide line to determine the 1-bit shift for the post-normalization in the Floating-point $n_{addition}$traction and multiplication.