• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.611-614
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• 2005

1970년대 말까지 초창기에 출시된 컴퓨터들은 부동 소수점을 표현하기 위한 자신들의 내부적 표현방식을 사용하였다. 따라서 각 컴퓨터마다 부동 소수점 연산에 대한 계산 결과가 약간씩 차이가 나기도 하였다. 이러한 문제점을 해결하기 위해 IEEE에서는 부동 소수점에 대한 표준안을 제안하였다. 이는 서로 다른 컴퓨터 간에 부동 소수점 데이터의 교환이 가능하게 할 뿐만 아니라 하드웨어 설계자들에게도 정확한 모델을 제공하는 것이 목적이었다. 이 당시 제정된 부동 소수점 표준안은 IEEE Standard 754 부동 소수점이며, 오늘날 인텔 CPU 기반의 PC, 매킨토시 및 대부분의 유닉스 플랫폼에서 컴퓨터 상의 실수를 표현하기 위해 사용하는 가장 일반적인 표현 방식으로 발전하였다. 본 논문에서는 부동 소수점의 기본적인 표현방식에 대해 연구하고, 이 중 32 bit 단일 정밀도 부동 소수점 가산기를 Microsoft Visual C++ 6.0을 이용해 시뮬레이션하고 이를 VHDL로 구현한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.11a
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• pp.377-380
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• 2002

신경회로망은 문자인식, 자동제어 등의 여러 분야에 널리 쓰이는 방식이다. 그러나 신경회로망을 구현하는데는 연산량이 많아서 실시간으로 구현하기에 어려움이 많이 따른다. 본 논문은 신경회로망을 구현하는데 필요한 연산을 살펴보고 그 연산을 구현하는 방법을 비교 분석하였다. 신경회로망을 구현하기 위해 DSP(Digital Signal Processor), PC의 FPU(Floating Point Unit), Intel사의 Pentium 계열 프로세서에서 지원하는 SIMD(Single Instruction Multiple Data) 기술을 사용하여 결과를 비교 분석 하였다. 신경회로망의 핵심인 MLP(Multi Layer Perceptron) 연산에 대해 실험한 결과 SIMD 기술을 이용하는 방법이 다른 방법에 비해 2배이상 좋은 결과를 나타내었다.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.11a
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• pp.197-199
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• 2012

Recently, a lot of general-purpose application programs in addition to graphic applications have been parallelized for boosting their performance using Graphic Processing Unit (GPU)'s excellent floating-point performance. In order to maximize the application performance on GPUs, optimizing the memory hierarchy and the on-chip caches such as the shared memory is essential. In this paper, we propose techniques to optimize the shared memory, and verify its effectiveness using a pattern matching application program.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.9
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• pp.724-733
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• 2003

Generally, dividers have been designed to use iteration, but recently the research on the pipelined divider is underway. It is a difficult point in the known pipelined division unit that a large lookup table is required. In this paper, the cost-effective pipelined divider is proposed, that needs a lookup table smaller than that of the other pipelined divider. The latency of the proposed divider is 3 cycles. We obtain a 30% reduced area than that of P. Hung.

• Journal of IKEEE
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• v.25 no.4
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• pp.762-765
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• 2021

In this paper, an automotive ECU (electronic control unit) with Kalman filter accelerator is designed and implemented. RISC-V is exploited as a processor core. Accelerator for Kalman filter matrix operation, CAN (controller area network) controller for in-vehicle network, and LIN (local interconnect network) controller are designed and embedded. Kalman filter operation consists of time update process and measurement update process. Current state variable and its error covariance are estimated in time update process. Final values are corrected from input measurement data and Kalman gain in measurement update process. Usually floating-point multiplication is exploited in software implementation, but fixed-point multiplier considering accuracy analysis is exploited in this paper to reduce hardware area. In 28nm silicon fabrication, its operating frequency, area, and gate counts are 100MHz, 0.37mm², and 760k gates, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.56-70
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• 2010

Rendering technique generating 2 dimensional image to give reality and high performance graphical processor for efficient processing of massive data are necessary to support realistic 3 dimensional graphical image. Recently, graphical hardwares have evolved rapidly. This enables high quality rendering effect that we were unable to process in realtime. Improving shading technique enabled us to render realistic images but still much time is required for this process. Multiple operational units are being integrated in a graphical processor for effective floating point operation using massive data to process almost real looking images. In this paper, we have designed and implemented a special functional unit to support high quality 3 dimensional computer graphic image on programmable integrated shader processor. We have done evaluation through functional level simulation of designed special functional unit. Hardware resource usage rate and execution speed are measured implementing directly on FPGA Virtex-4(xc4vlx200).

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.6
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• pp.147-155
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• 1989

In this paper, a real-time implementation of the TWS(track-while-scan) system using the high-speed DSP (digital signal processor) TMS320C25 is described. First, attempts have been made to investigate the FWL (finite word length) effect, which is caused by employing a fixed point arithmetic, of implementing the Kalman filter. The real-time TWS system consists of TWS arithmetic unit, scan converter, and system controller. In addition, the TWS system is in tegrated in the Multi-Bus. In experiment, it is observed that by employing the floating point arithmetic the computation time of 0.35sec is required for tracking 8 targets simultaneously, while 0.28sec is required for the fixed point arithmetic. Since the TWS system is designed to track up to 8 targets simultaneously, we conclude that the system is enough to process Kalman filter in a real-time.

• 한국HCI학회:학술대회논문집
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• 2007.02a
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• pp.982-987
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• 2007

The necessity of data compression scheme for volume data has been increased because of the increase of data capacity and the amount of network uses. Now we have various kinds of compression schemes, and we can choose one of them depending on the data types, application fields, the preferences, etc. However, the capacity of data which is produced by application scientists has been excessively increased, and the format of most scientific data is 3D volume. For 2D image or 3D moving pictures, many kinds of standards are established and widely used, but for 3D volume data, specially time-varying volume data, it is very difficult to find any applicable compression schemes. In this paper, we present a compression scheme for encoding time-varying volume data. This scheme is aimed to encoding time-varying volume data for visualization. This scheme uses MPEG's I- and P-frame concept for raising compression ratio. Also, it transforms volume data using Daubechies D4 filter before encoding, so that the image quality is better than other wavelet-based compression schemes. This encoding scheme encodes time-varying volume data composed of single precision floating-point data. In addition, this scheme provides the random reconstruction accessibility for an unit, and can be used for compressing large time-varying volume data using correlation between frames while preserving image qualities.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.140-142
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• 2011

In this paper, special purpose arithmetic unit for mobile graphics accelerator is designed. The designed processor supports six operations, such as $1/{\chi}$, $\frac{1}{{\sqrt{x}}$, $log_2x$, $2^x$, $sin(x)$, $cos(x)$. The processor adopts 2nd-order polynomial minimax approximation scheme based on IEEE floating point data format to satisfy accuracy conditions and has 5-stage pipeline structure to meet high operational rates. The SFAU processor consists of 23,000 gates and its estimated operating frequency is about 400 Mhz at operating condition of 65nm CMOS technology. Because the processor can execute all operations with 5-stage pipeline scheme, it has about 400 MOPS(million operations per second) execution rate. Thus, it can be applicable to the 3D mobile graphics processors.

• Journal of Korean Library and Information Science Society
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• v.4
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• pp.61-90
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• 1977

The historical development of books examination with utilizing science become inevitable to the machanization of library catalogues. With the advance of times, like this, a new- development of $Indention('||'&'||'$ : Kisun) must be sought for which is a kind of descriptive catalogues being used now. This paper is scheduled to grasp problems in the course of using and logical grounds of Indention which hal-e been used disordering. It must be considered that four kinds of Icdention settlement is suitable to the features of Korean letters. 1) TI-e must consider the features of Korean Language and Oriental Language writing(Japan, China). There must be a establishment of floating $Indention('||'&'||'E$ : Kisun), which are suitable for the writting style or hand writting man on the point of most of Koreans are depend upon hand witting, then books catalogues like western language, not left edge of the cards of the $Indention(B$ : Kisun) establishing, from edge to Call Number, from the last of the Call Number to First Indention(%-Bl63). First Indention(%-%%) to a space of Second $indention($\ulcorner^%)$ must be established and then, every catalogue and Indentions are distinguished surely. 2) \Then we consider the developing catalogue making in the future. It is important to establish a fixed $Indention('||'&'||'$ : Kisun) for machinization of typewriter(Korean, Mimeographing) and computer, etc ... not "Cm" unit but "Space" unit, and consider oriental letter, ne make more surplus space as a Indention, we can give anadaptablity of using machines. 3) Considering typography printing and type-setting printing by printing type, we must fit the $Indention(\ulcorner'||'&'||'$ : Kisun) as a "Cm" unit, and there must be a re-adjustment of $Indention(g$$ : Kisun) which considered the complexity of Call Number by a mass of collecting books like this, the establishment of Indention(E'||'&'||'j!: Kisun). We must not use a uilified one as a concrete conception by "Space" or "Cm" unit which has been used now but re-adjusted adaptably which can be fited as a method of making of catalogues. 4) The name of $Indcntion(J, S$ : Kisun) has becll called 7;arious methods until now, but English Indention which has been used without any concrete mexirig must be used as a ours fitable as a our mind. The above mentioned is presented as a Indention and examinational l~letilods by myself style, I wants these r i l l be helpful to the future developments of the machanization of Indention $(sf:$ Ki sun). Concrete studies must be continued in the future for development of $Indention(zj:$ : Kisun). : Kisun).