• Title/Summary/Keyword: Floating-Point Unit

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Design of a Floating Point Unit for 3D Graphics Geometry Engine (3D 그래픽 Geometry Engine을 위한 부동소수점 연산기의 설계)

  • Kim, Myeong Hwm;Oh, Min Seok;Lee, Kwang Yeob;Kim, Won Jong;Cho, Han Jin
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.10 s.340
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    • pp.55-64
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    • 2005
  • In this paper, we designed floating point units to accelate real-time 3D Graphics for Geometry processing. Designed floating point units support IEEE-754 single precision format and we confirmed 100 MHz performance of floating point add/mul unit, 120 MHz performance of floating point NR inverse division unit, 200 MHz performance of floating point power unit, 120 MHz performance of floating point inverse square root unit at Xilinx-vertex2. Also, using floating point units, designed Geometry processor and confirmed 3D Graphics data processing.

A Design of High Speed Floating Point Unit (고속 Floating Point Unit 설계)

  • Oh, Haeng-Soo
    • Journal of the Institute of Electronics Engineers of Korea TE
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    • v.39 no.2
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    • pp.1-5
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    • 2002
  • Floating point unit system follows IEEE 754 Standard. In this paper, we used 1's complement system instead of 2's complement to practice the arithmetic. By converting we enable this system to compute simply and fast. To improve the speed of newly design adder, we used a transformation Carry selector adder of 53 bits. In paper, a design of floating point unit high efficiency micro processor system about for high speed. 

A Design of 24-bit Floating Point MAC Unit for Transformation of 3D Graphics (3차원 그래픽의 트랜스포메이션을 위한 24-bit 부동 소수점 MAC 연산기의 설계)

  • Lee, Jungwoo;Kim, Woojin;Kim, Kichul
    • IEMEK Journal of Embedded Systems and Applications
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    • v.4 no.1
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    • pp.1-8
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    • 2009
  • This paper proposes a 24-bit floating point multiply and accumulate(MAC) unit that can be used in geometry transformation process in 3D graphics. The MAC unit is composed of floating point multiplier and floating point accumulator. When separate multiplier and accumulator are used, matrix calculation, used in the transformation process, can't use continuous accumulation values. In the proposed MAC unit the accumulator can get continuous input from the multiplier and the calculation time is reduced. The MAC unit uses about 4,300 gates and can be operated at 150 MHz frequency.

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Algebraic Accuracy Verification for Division-by-Convergence based 24-bit Floating-point Divider Complying with OpenGL (Division-by-Convergence 방식을 사용하는 24-비트 부동소수점 제산기에 대한 OpenGL 정확도의 대수적 검증)

  • Yoo, Sehoon;Lee, Jungwoo;Kim, Kichul
    • Journal of IKEEE
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    • v.17 no.3
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    • pp.346-351
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    • 2013
  • Low-cost and low-power are important requirements in mobile systems. Thus, when a floating-point arithmetic unit is needed, 24-bit floating-point format can be more useful than 32-bit floating-point format. However, a 24-bit floating-point arithmetic unit can be risky because it usually has lower accuracy than a 32-bit floating-point arithmetic unit. Consecutive floating-point operations are performed in 3D graphic processors. In this case, the verification of the floating-point operation accuracy is important. Among 3D graphic arithmetic operations, the floating-point division is one of the most difficult operations to satisfy the accuracy of $10^{-5}$ which is the required accuracy in OpenGL ES 3.0. No 24-bit floating-point divider, whose accuracy is algebraically verified, has been reported. In this paper, a 24-bit floating-point divider is analyzed and it is algebraically verified that its accuracy satisfies the OpenGL requirement.

A Study on High Performances Floating Point Unit (고성능 부동 소수점 연산기에 대한 연구)

  • Park, Woo-Chan;Han, Tack-Don
    • The Transactions of the Korea Information Processing Society
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    • v.4 no.11
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    • pp.2861-2873
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    • 1997
  • An FPU(Floating Point unit) is the principle component in high performance computer and is placed on a chip together with main processing unit recently. As a Processing speed of the FPU is accelerated, the rounding stage, which occupies one of the floating point Processing steps for floating point operations, has a considerable effect on overall floating point operations. In this paper, by studying and analyzing the processing flows of the conventional floating point adder/subtractor, multipler and divider, which are main component of the FPU, efficient rounding mechanisms are presented. Proposed mechanisms do not require any additional execution time and any high speed adder for rounding operation. Thus, performance improvement and cost-effective design can be achieved by this approach.

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Design of a high-performance floating-point unit adopting a new divide/square root implementation (새로운 제산/제곱근기를 내장한 고성능 부동 소수점 유닛의 설계)

  • Lee, Tae-Young;Lee, Sung-Youn;Hong, In-Pyo;Lee, Yong-Surk
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.12
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    • pp.79-90
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    • 2000
  • In this paper, a high-performance floating point unit, which is suitable for high-performance superscalar microprocessors and supports IEEE 754 standard, is designed. Floating-point arithmetic unit (AU) supports all denormalized number processing through hardware, while eliminating the additional delay time due to the denormalized number processing by proposing the proposed gradual underflow prediction (GUP) scheme. Contrary to the existing fixed-radix implementations, floating-point divide/square root unit adopts a new architecture which determines variable length quotient bits per cycle. The new architecture is superior to the SRT implementations in terms of performance and design complexity. Moreover, sophisticated exception prediction scheme enables precise exception to be implemented with ease on various superscalar microprocessors, and removes the stall cycles in division. Designed floating-point AU and divide/square root unit are integrated with and instruction decoder, register file, memory model and multiplier to form a floating-point unit, and its function and performance is verified.

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A Study on the Behavior of Floating-Point Unit Conforming the ANSI/IEEE Std. 754-1985 (ANSI/IEEE Std. 754-1985에 의거한 부동소수점 연산기의 동작원리에 관한 연구)

  • Kim, Kwang-Uk;Chung, Tae-Sang
    • Proceedings of the KIEE Conference
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    • 1999.11c
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    • pp.788-790
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    • 1999
  • A software implementation of floating-point addition and multiplication is presented. For this, the ANSI/IEEE standard for binary floating-point arithmetic is reviewed briefly. The architecture and behavior of the $Intel^{(R)}\;80{\times}87$ FPU is fully studied and basic algorithms for floating-point addition and multiplication are used for the implementation. Some examples and their verifications are also presented.

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Design of a Floating Point Multiplier for IEEE 754 Single-Precision Operations (IEEE 754 단정도 부동 소수점 연산용 곱셈기 설계)

  • Lee, Ju-Hun;Chung, Tae-Sang
    • Proceedings of the KIEE Conference
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    • 1999.11c
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    • pp.778-780
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    • 1999
  • Arithmetic unit speed depends strongly on the algorithms employed to realize the basic arithmetic operations.(add, subtract multiply, and divide) and on the logic design. Recent advances in VLSI have increased the feasibility of hardware implementation of floating point arithmetic units and microprocessors require a powerful floating-point processing unit as a standard option. This paper describes the design of floating-point multiplier for IEEE 754-1985 Single-Precision operation. Booth encoding algorithm method to reduce partial products and a Wallace tree of 4-2 CSA is adopted in fraction multiplication part to generate the $32{\times}32$ single-precision product. New scheme of rounding and sticky-bit generation is adopted to reduce area and timing. Also there is a true sign generator in this design. This multiplier have been implemented in a ALTERA FLEX EPF10K70RC240-4.

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A design of floating-point arithmetic unit for superscalar microprocessor (수퍼스칼라 마이크로프로세서용 부동 소수점 연산회로의 설계)

  • 최병윤;손승일;이문기
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.21 no.5
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    • pp.1345-1359
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    • 1996
  • This paper presents a floating point arithmetic unit (FPAU) for supescalar microprocessor that executes fifteen operations such as addition, subtraction, data format converting, and compare operation using two pipelined arithmetic paths and new rounding and normalization scheme. By using two pipelined arithmetic paths, each aritchmetic operation can be assigned into appropriate arithmetic path which high speed operation is possible. The proposed normalization an rouding scheme enables the FPAU to execute roundig operation in parallel with normalization and to reduce timing delay of post-normalization. And by predicting leading one position of results using input operands, leading one detection(LOD) operation to normalize results in the conventional arithmetic unit can be eliminated. Because the FPAU can execuate fifteen single-precision or double-precision floating-point arithmetic operations through three-stage pipelined datapath and support IEEE standard 754, it has appropriate structure which can be ingegrated into superscalar microprocessor.

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A Variable Latency K'th Order Newton-Raphson's Floating Point Number Divider (가변 시간 K차 뉴톤-랍손 부동소수점 나눗셈)

  • Cho, Gyeong-Yeon
    • IEMEK Journal of Embedded Systems and Applications
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    • v.9 no.5
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    • pp.285-292
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    • 2014
  • The commonly used Newton-Raphson's floating-point number divider algorithm performs two multiplications in one iteration. In this paper, a tentative K'th Newton-Raphson's floating-point number divider algorithm which performs K times multiplications in one iteration is proposed. Since the number of multiplications performed by the proposed algorithm is dependent on the input values, the average number of multiplications per an operation in single precision and double precision divider is derived from many reciprocal tables with varying sizes. In addition, an error correction algorithm, which consists of one multiplication and a decision, to get exact result in divider is proposed. Since the proposed algorithm only performs the multiplications until the error gets smaller than a given value, it can be used to improve the performance of a floating point number divider unit. Also, it can be used to construct optimized approximate reciprocal tables.