• Journal of IKEEE
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• v.24 no.4
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• pp.1156-1161
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• 2020

In this paper, we propose a new ESD protection circuit with improved electrical characteristics through structural changes of the existing one-way SCR. The proposed ESD protection circuit has high holding voltage characteristics due to the inserted N+ floating and P+ floating regions, and thus the latch-up immunity characteristics are improved. In addition, structural change enables ESD discharge in four types of Zapping mode (PD, PS, ND, NS), and has superior area efficiency than unidirectional SCR. In addition, the P+ floating and N+ floating lengths corresponding to the base length of the parasitic bipolar transistor, and the distance between P+ floating and N+ floating were designated as design variables, and the high holding voltage was verified through Synopsys' TCAD Simulator.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.5
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• pp.423-430
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• 2005

In this paper, we have simulated a Symmetric Dual-gate Single-Si TFT which has three split floating $n^{+}$ zones. This structure reduces the kink-effect drastically and improves the on-current. Due to the separated floating $n^{+}$ zones, the transistor channel region is split into four zones with different lengths defined by a floating $n^{+}$ region. This structure allows an effective reduction of the kink-effect depending on the length of two sub-channels. The on-current of the proposed dual-gate structure is 0.9 mA while that of the conventional dual-gate structure is 0.5 mA at a 12 V drain voltage and a 7 V gate voltage. This results show a $80 {\%}$ enhancement in on-current by adding two floating $n^{+}$ zones. Moreover we observed the reduction of electric field In the channel region compared to conventional single-gate TFT and the reduction of the output conductance in the saturation region. In addition we also confirmed the reduction of hole concentration in the channel region so that the kink-effect reduces effectively.

• Environmental Engineering Research
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• v.22 no.2
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• pp.210-215
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• 2017

Produced water is the largest wastestream of oil and gas exploration. It consists of various organic and inorganic compounds that hinder its beneficial use. This study compared the treatment of produced water in a batch suspended and biofilm activated sludge process. The biofilm carrier material was made from Gardenia Carinata shell. COD, $NH_4{^+}-N$ and $NO_3-N$ removal was monitored in both the suspended (control) and floating carrier bioreactors. The results show a rapid reduction of produced water constituents in the floating carrier bioreactor. COD, $NH_4{^+}-N$ and $NO_3-N$ removal was in the range of 99%, 98% and 97% for the floating carrier bioreactor whereas it was 88%, 84% and 83% for the control bioreactor. The rapid reduction of COD, $NH_4{^+}-N$ and $NO_3-N$ clearly indicate that the floating carrier materials served as an attached growth medium for microorganisms, improved the breakdown of produced water constituents and reduced inhibition of microbial metabolic activities.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.3
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• pp.24-30
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• 1995

The process of conventional floating-point additio $n_traction operation consists of alignment, additio $n_traction, normalization, and rounding stage. Because rounding stage needs an incrementor or adder, it occupies much time and chip area. In addition, it needs additional time and hardware for renormalization which occurs in overflow due to rounding In this paper, floating-point adde $r_tractor performing rounding and additio $n_traction in parallel is presented by using the feature of additio $n_traction and carry select adder used in additio $n_tracting stage. Proposed floating point adde $r_tractor doesn't need time and incrementor nor adder for rounding. Also, renormalization doesn't occur since rounding is performed prior to normalization.to normalization.

• Journal of the Korea Computer Industry Society
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• v.6 no.5
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• pp.783-790
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• 2005

In this paper, we have simulated a Symmetric Dual-gate Single-Si TFT which has three split floating n+ zones. This structure reduces the kink-effect drastically and improves the on-current. Due to the separated floating n+ zones, the transistor channel region is split into four zones with different lengths defined by a floating n+ region, This structure allows an effective reduction of the kink-effect depending on the length of two sub-channels. The on-current of the proposed dual-gate structure is 0.9mA while that of the conventional dual-gate structure is 0.5mA at a 12V drain voltage and a 7V gate voltage. This result shows a 80% enhancement in on-current. Moreover we observed the reduction of electric field in the channel region compared to conventional single-gate TFT and the reduction of the output conductance in the saturation region. In addition, we also confirmed the reduction of hole concentration in the channel region so that the kink-effect reduces effectively.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.1
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• pp.45-51
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• 2018

In this paper, a tentative Kth order Newton-Raphson's floating point number Nth root algorithm for K order convergence rate in one iteration is proposed by applying Taylor series to the Newton-Raphson root algorithm. Using the proposed algorithm, $F^{-1/N}$ and $F^{-(N-1)/N}$ can be computed from iterative multiplications without division. It also predicts the error of the algorithm iteration and iterates only until the predicted error becomes smaller than the specified value. Since the proposed algorithm only performs the multiplications until the error gets smaller than a given value, it can be used to improve the performance of a floating point number Nth root unit.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1017-1020
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• 1998

We propose an algorithm which processes the floating-point $n_{addition}$traction and rounding in parallel. It also processes multiplication and rounding in the same way. The hardware model is presented that minimizes the delay time to get results for all the rounding modes defined in the IEEE Standards. An unified method to get the three bits(L, G, S)for the rounding is described. We also propose an unified guide line to determine the 1-bit shift for the post-normalization in the Floating-point $n_{addition}$traction and multiplication.

• International Journal of Naval Architecture and Ocean Engineering
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• v.8 no.3
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• pp.252-261
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• 2016

A spar-type floating substructure that is being widely used for offshore wind power generation is vulnerable to resonance in the heave direction because of its small water plane area. For this reason, the stable dynamic response of this floating structure should be ensured by accurately identifying the resonance characteristics. The purpose of this study is to analyze the characteristics of the combination resonance between the excitation frequency of a regular wave and natural frequencies of the floating substructure. First, the nonlinear equations of motion with two degrees of freedom are derived by assuming that the floating substructure is a rigid body, where the heaving motion and pitching motions are coupled. Moreover, to identify the characteristics of the combination resonance, the nonlinear term in the nonlinear equations is approximated up to the second order using the Taylor series expansion. Furthermore, the validity of the approximate model is confirmed through a comparison with the results of a numerical analysis which is made by applying the commercial software ANSYS AQWA to the full model. The result indicates that the combination resonance occurs at the frequencies of ${\omega}{\pm}{\omega}_5$ and $2{\omega}_{n5}$ between the excitation frequency (${\omega}$) of a regular wave and the natural frequency of the pitching motion (${\omega}_{n5}$) of the floating substructure.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.4
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• pp.199-204
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• 2016

This paper was proposed floating island power MOSFET for lowering on state resistance and the proposed device was maintained 600 V breakdown voltage. The electrical field distribution of floating island power MOSFET was dispersed to floating island between P-base and N-drift. Therefore, we designed higher doping concentration of drift region than doping concentration of planar type power MOSFET. And so we obtain the lower on resistance than on resistance of planar type power MOSFET. We needed the higher doping concentration of floating island than doping concentration of drift region and needed width and depth of floating island for formation of floating island region. We obtained the optimal parameters. The depth of floating island was $32{\mu}m$. The doping concentration of floating island was $5{\times}1,012cm^2$. And the width of floating island was $3{\mu}m$. As a result of designing the floating island power MOSFET, we obtained 723 V breakdown voltage and $0.108{\Omega}cm^2$ on resistance. When we compared to planar power MOSFET, the on resistance was lowered 24.5% than its of planar power MOSFET. The proposed device will be used to electrical vehicle and renewable industry.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.156-161
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• 2017

This work presents a novel structure for junction-less tunneling field effect transistor (JL-TFET) with a floating gate over the source region. Introduction of floating gate instead of fixed metal gate removes the limitation of fabrication process suitability. The proposed device is based on a heavily n-type-doped Si-channel junction-less field effect transistor (JLFET). A floating gate over source region and a control-gate with optimized metal work-function over channel region is used to make device work like a tunnel field effect transistor (TFET). The proposed device has exhibited excellent ID-VGS characteristics, ION/IOFF ratio, a point subthreshold slope (SS), and average SS for optimized device parameters. Electron charge stored in floating gate, isolation oxide layer and body doping concentration are optimized. The proposed JL-TFET can be a promising candidate for switching performances.