• ETRI Journal
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• 제36권6호
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• pp.942-952
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• 2014

This paper presents a novel test point insertion (TPI) method for a pseudo-random built-in self-test (BIST) to reduce the area overhead. Recently, a new TPI method for BISTs was proposed that tries to use functional flip-flops to drive control test points instead of adding extra dedicated flip-flops for driving control points. The replacement rule used in a previous work has limitations preventing some dedicated flip-flops from being replaced by functional flip-flops. This paper proposes a logic cone analysis-based TPI approach to overcome the limitations. Logic cone analysis is performed to find candidate functional flop-flops for replacing dedicated flip-flops. Experimental results indicate that the proposed method reduces the test point area overhead significantly with minimal loss of testability by replacing the dedicated flip-flops.

• 국제물리치료학회지
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• 제4권2호
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• pp.562-565
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• 2013

The fact that flip-flops, one of many different types of unstable shoes, are light and relatively easy to put on, accounts for their popularity among people. But because flip-flops rely heavily on the support of a single thong between your first and second toes, they impose a huge amount of pressure onto lower leg. Thus in the following experiment we tried to examine the different effects of flip-flops and running shoes in terms of their effect on muscle activity and fatigue of tibialis anterior and gastrocnemius during walking. In order to measure an electromyogram we used Free EMG system. 10 men and 10 women in running shoes ran on treadmills for 15 minutes at 4.8km/h, 2 days later the same experiment was carried out, but this time, in flip-flops. p value turned out to be greater than .05 and thus there was no considerable difference between the effects of flip-flops and running shoes on muscle activity and fatigue during walking. Therefore we conclude that despite the fact that flip-flops are considered unstable, their effects on muscle activity and fatigue of tibialis anterior and gastrocnemius are negligible.

• 전자공학회논문지C
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• 제35C권12호
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• pp.49-58
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• 1998

본 논문에서는 무고정 부분 스캔 테스트 방법을 위한 새로운 스캔 선택 알고리즘에 대하여 논한다. 무고정 부분 스캔 테스트 방법은 모든 플립-플롭을 스캔하지 않는다는 점을 제외하면 완전 스캔과 동일한 테스트 방법이다. 이 테스트 방법은 테스트 벡터를 입력, 인가, 혹은 적용 등, 어느 때에도 스캔, 비스캔 중 어느 플립-플롭의 데이터 값도 고정하지 않는다. 제안된 스캔 선택 알고리즘은 무고정 부분 스캔 테스트 방법에서 완전 스캔 고장 검출율을 거의 유지하면서 많은 플립-플롭을 스캔하지 않게 한다.

• 대한전자공학회논문지SD
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• 제42권8호
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• pp.35-42
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• 2005

본 논문에서는 전력소모 감소 및 강건성 (robustness) 향상을 위한 새로운 구조의 플립-플롭을 제안한다. 가변 샘플링 윈도우 플립-플롭(Variable sampling window flip-flop, VSWFF)은 입력 데이터에 따라 샘플링 윈도우의 폭을 변화시켜 강인한 데이터-래치 동작을 제공할 뿐 아니라 더욱 짧은 hold time을 갖는다. 또한, 이 플립-플롭은 입력 스위칭 행위(input switching activity)가 큰 경우에 기존의 저전력 플립-플롭보다 내부 전력소모를 감소시킬 수 있다. 클럭 진폭 감쇄형 가변 샘플링 윈도우 플립-플롭(Clock swing-reduced variable sampling window flip-flop, CSR-VSWFF)은 작은 스윙 폭의 클럭을 사용함으로써 클럭분배망(clock distribution network)의 전력소모를 감소시킬 수 있다. 기존의 클럭 진폭 감쇄형 플립-플롭(Reduced clock swing flip-flop, RCSFF)과 달리, 제안된 플립-플롭은 공급전압만으로 동작하므로 고전압의 발생 및 분배로 인한 설계 상의 비용증가를 제거한다. 시뮬레이션 결과, 기존의 플립-플롭과 비교하여 더욱 좁은 샘플링 윈도우에서도 불변의 지연값(latency) 을 유지하고 전력-지연 곱(power-delay product, PDP)이 개선됨을 확인하였다. 제안된 플립-플롭의 성능을 평가하기 위하여 $0.3\mu m$ CMOS 공정기술을 이용하여 테스트 칩을 설계하였으며, 실험 결과, VSWFF는 입력 스위칭 행위가 최대일 때 전력소모가 감소하며 CSR-YSWFF를 이용하여 설계된 동기 카운터는 부가 고전압의 사용 없이 전력소모가 감소됨을 확인하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.779-782
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• 1998

This paper describes a high-speed Dual-modulus Prescaler (DMP) for RF mobile communication systems with pulse remover using selective latch technique. This circuit achieves high speed and low power consumption by reducing full speed flip-flops and using a selective latch. The proposed DMP consists of only one full speed flip-flop, a selective latch, conventional flip-flops, and a control gate. In order to ensure the timing of control signal, duty cycle problem and propagation delay must be considered. The failling edgetriggered flip-flops alleviate the duty cycle problem andthis paper shows that the propagation delay of control signal doesn't matter. The maximum operating frequency of the proposed DMP with 0.6um CMOS technology is up to 2.2㎓ at 3.3V power supply and the circuit consumes 5.24mA.

• 한국정보처리학회논문지
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• 제4권5호
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• pp.1371-1379
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• 1997

본 논문에서는 순차화로에서의 시험 불가능 고장을 찾는 새로운 알고리즘을 제시 하였다. 이 알고리즘에서는 초기화가 불가능한 플플롭을 먼저 찾으면서 이 과정에서 이 플립플롭의 초기화를 막는 고장, FPI를 찾고 이 고장의 전파 경로를 검색한다. 또한 이 알고리즘을 ISCA889 벤츠마크 회로를 대상으로 적용하여 시험 불가능한 FPI의 갯수를 제시하였다. 테스트 생성에 소요되는 시간의 대부분이 시험 불가능고장의 검출에 사용 되는 것을 고려할 때, 이 알고리즘을 테스트 생성기의 전처리 과정으로 사용하면, 테스트 생성기의 효율을 크게 높일 것으로 기대된다.

• 전자공학회논문지C
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• 제35C권3호
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• pp.1-15
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• 1998

In this paper, we propose a partial scan test method which can be applied to large VLSI designs. In this method, it is not necessary to hold neither scanned nor unscanned flip-flops during scan in, test application,or scan out. This test method requires almost identical design for testability modification and test wave form when compared to the full scan test method, and the method is applicable to large VLSI chips. The well known FAN algorithm has been modified to devise to sequential ATPG algorithm which is effective for the proposed test method. In addition, a partial scan algorithm which is effective for the proposed test method. In addition, a partial algorithm determined a maximal set of flip-flops which gives high fault coverage when they are unselected. The experimental resutls show that the proposed method allow as large as 20% flip-flops to remain unscanned without much decrease in the full scan fault coverage.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.279-282
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• 1999

Frequency divider selects the channel of the frequency synthesizer. General programmable divider has many flip-flops to realize all integer division value and stability problem by using dual modules prescaler. In this paper, a new architecture of programmable divider is proposed and designed to improve these problems. The proposed programmable divider has only thirteen flip-flops. The programmable divider is designed by 0.65${\mu}{\textrm}{m}$ CMOS technology and HSPICE. Operating frequency of the programmable divider is 200MHz with a 3V supply voltage.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 2000년도 High Temperature Superconductivity Vol.X
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• pp.160-164
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• 2000

Digital to analog converters based on the Josephson effect are promising for voltage standard, because they produce voltage steps with high precision and good stability. In this paper, we made a simulation study on RSFQ D/A converter. RSFQ D/A converter was composed of NDRO cells, T(toggle) flip-flops, D flip-flops, Splitters and Confluence Buffers. Confluence Buffer was used to reset the D/A converter. We also obtained operating margins of the important circuit values by simulational experiments.

• Progress in Superconductivity
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• 제3권2호
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• pp.172-177
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• 2002

Superconductive digital to analog converters (DAC) based on Josephson effect produce the voltage steps with high precision and good stability Therefore, they can be applied to obtain a very accurate ac voltage standard. In this paper, we made a simulation study of Rapid Single Flux Quantum (RSFQ) DAC. RSFQ DAC was composed of Non-destructive Head Out (NDRO) cells, T flip-flops, D flip-flops, Splitters, and Confluence Buffers. Confluence Buffer was used in resetting the DACs. We also obtained operating margins of the important circuit parameters in simulations.