• 마이크로전자및패키징학회지
• /
• 제12권4호통권37호
• /
• pp.315-321
• /
• 2005

교류자기장에 의한 유도가열체를 이용하여 LCD 평판 디스플레이 패널의 가열을 최소화하면서 IC 칩을 실장시킬 수 있는 COG 접속기술에 대해 연구하였다. 크기 5mm${\times}$5mm, 두께 $600{\mu}m$의 Cu 도금막으로 제조한 유도가열체에 14 kHz, 230 Oe의 교류자기장을 인가시 60초 이내에 유도가열체의 온도가 Sn-3.5Ag 무연솔더의 리플로우에 필요한 $250^{\circ}C$에 도달하였으며, 유도가열체로부터 2 mm 떨어진 부위에서부터 기판의 온도는 $100^{\circ}C$ 이하로 유지되었다. 이와 같은 Cu 도금막 유도가열체에 14 kHz, 230 Oe의 교류자기장을 120초 동안 인가하여 Sn-3.5Ag 솔더범프를 리플로우 시켜 COG 실장을 하는 것이 가능하였다.

• 대한용접접합학회:학술대회논문집
• /
• 대한용접접합학회 2010년도 춘계학술발표대회 초록집
• /
• pp.78-78
• /
• 2010

모바일 정보통신기기를 중심으로 패키지의 초소형화, 고집적화를 위해 플립칩 공법의 적용이 증가되고 있고 있으며 접속피치의 미세화에 따라 솔더 및 언더필을 사용하는 C4 공법보다 ACA(Anisotropic Conductive Adhesive), NCA (Non-conductive Adhesive) 등의 접착제를 이용하는 칩본딩 공법에 대한 요구가 증가하고 있다. 특히, NCA 공법의 경우 산업 현장의 대량생산에 대응하기 위해서는 접착제의 속경화 특성이 요구되어 진다. 일반적으로 접착제의 경화거동은 DSC(Differential Scanning Calorimeter)를 사용해 확인하지만, 수초 이내에 경화되는 접착제의 경우는 적용되기 어렵다. 본 연구에서는 이러한 전자패키지용 접착제의 속경화 거동을 효과적으로 평가할 수 있는 방법을 조사 하였다. 실험에서 사용된 접착제는 에폭시계 레진 기반에 이미다졸계 경화제를 사용한 기본적인 포뮬레이션을 사용하였고, 경화시간은 160^{\circ}C에서 1분 이내에 경화되는 특성을 가지고 있다. 경화 거동을 확인하기 위해서 isothermal DSC와 DEA(Dielectric Analysis)의 두가지 방법을 사용해 비교하였다. 두 실험 방법 모두 $160^{\circ}C$를 유지하며 경화 거동을 확인하였고, DoC(Degree of Cure)의 측정오차를 비교 분석하였다. DEA는 이온 모빌리티 변화에 따른 유전손실율을 측정하는 방법으로 80~90% 이후의 경화도는 측정되지 않았지만, 수초 이내에 경화되는 속경화 특성을 평가하기에 적합한 것으로 확인되었다.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2005년도 추계학술대회 논문집 전기물성,응용부문
• /
• pp.30-32
• /
• 2005

This paper reports on an LTCC-based packaging method using Au/Sn eutectic bonding process for RF MEMS applications. The proposed packaging structure was realized by a micromachining technology. An LTCC substrate consists of metal filled vertical via feedthroughs for electrical interconnection and Au/Sn sealing rim for eutectic bonding. The LTCC capping substrate and the glass bottom substrate were aligned and bonded together by a flip-chip bonding technology. From now on, shear strength and He leak rate will be measured then the fabricated package will be compared with the LTCC package using BCB adhesive bonding method which has been researched in our previous work.

• 마이크로전자및패키징학회지
• /
• 제12권2호
• /
• pp.111-119
• /
• 2005

직경 $75{\mu}m$ 높이 $90{\mu}m$및 $150{\mu}m$ 피치의 Cu via를 통한 삼차원 배선구조를 갖는 스택 시편을 deep RIE를 이용한 via hole 형성공정 , 펄스-역펄스 전기도금법에 의한 Cu via filling 공정, CMP를 이용한 Si thinning 공정, photholithography, 금속박막 스퍼터링, 전기도금법에 의한 Cu/Sn 범프 형성공정 및 플립칩 공정을 이용하여 제작하였다. Cu via를 갖는 daisy chain 시편에서 측정한 접속범프 개수에 따른 daisy chain의 저항 그래프의 기울기로부터 Cu/Sn 범프 접속저항과 Cu via 저항을 구하는 것이 가능하였다. $270^{\circ}C$에서 2분간 유지하여 플립칩 본딩시 $100{\times}100{\mu}m$크기의 Cu/Sn 범프 접속저항은 6.7 m$\Omega$이었으며, 직경 $75 {\mu}m$, 높이 $90{\mu}m$인 Cu via의 저항은 2.3m$\Omega$이었다.

• 대한금속재료학회지
• /
• 제47권7호
• /
• pp.447-453
• /
• 2009

Isotropic conductive adhesives (ICAs) have been used or considered as an interconnect material for radio frequency identification (RFID) inlays or other flip chip assemblies due to the advantages of having a low temperature and high-speed bonding. In this work, the curing properties of commercial ICAs for the RFID tag application and the signal transmission in conductive lines that contained the ICA joints were evaluated as a function of the degree of cure at 900 MHz frequency range. The ICAs showed adequate signal transmission only after the curing process passed over the critical time. It was also found that the insertion loss of signal was more dependent on the contact states of Ag fillers in the bondline in preference to the electrical resistance of the ICA itself.

• ETRI Journal
• /
• 제37권2호
• /
• pp.387-394
• /
• 2015

A novel interconnection technology based on a 52InSn solder was developed for flexible display applications. The display industry is currently trying to develop a flexible display, and one of the crucial technologies for the implementation of a flexible display is to reduce the bonding process temperature to less than $150^{\circ}C$. InSn solder interconnection technology is proposed herein to reduce the electrical contact resistance and concurrently achieve a process temperature of less than $150^{\circ}C$. A solder bump maker (SBM) and fluxing underfill were developed for these purposes. SBM is a novel bumping material, and it is a mixture of a resin system and InSn solder powder. A maskless screen printing process was also developed using an SBM to reduce the cost of the bumping process. Fluxing underfill plays the role of a flux and an underfill concurrently to simplify the bonding process compared to a conventional flip-chip bonding using a capillary underfill material. Using an SBM and fluxing underfill, a $20{\mu}m$ pitch InSn solder SoP array on a glass substrate was successfully formed using a maskless screen printing process, and two glass substrates were bonded at $130^{\circ}C$.

• 한국표면공학회지
• /
• 제50권3호
• /
• pp.170-176
• /
• 2017

EPIG (Electroless Pd/immersion Au) process was studied to replace ENIG (electroless Ni/immersion Au) and ENEPIG (electroless Ni/electroless Pd/immersion Au) processes for bump surface treatment used in high reliable flip chip packages. The palladium and gold layers formed by EPIG process were uniform with thickness of 125 nm and 34.5 nm, respectively. EPAG (Electroless Pd/autocatalytic Au) also produced even layers of palladium and gold with the thickness of 115 nm and 100 nm. TEM results exhibited that the gold layer in EPIG surface had crystalline structure while the palladium layer was amorphous one. After annealing at 250 nm, XPS analysis indicated that the palladium layer with thickness more than 22~33 nm could act as a diffusion barrier of copper interconnects. As a result of comparing the chip shear strength obtained from ENIG and EPIG surfaces, it was confirmed that the bonding strength was similar each other as 12.337 kg and 12.330 kg, respectively.

• 마이크로전자및패키징학회지
• /
• 제26권4호
• /
• pp.47-53
• /
• 2019

Polydimethylsiloxane (PDMS)를 베이스 기판으로 사용하고 이보다 강성도가 높은 polytetrafluoroethylene(PTFE)를 island 기판으로 사용한 soft PDMS/hard PDMS/PTFE 구조의 강성도 경사형 신축 패키지를 형성하고, 이의 신축변형에 따른 저항특성을 분석하였다. PDMS/PTFE 기판패드에 50 ㎛ 직경의 칩 범프들을 anisotropic conductive paste를 사용하여 실장한 플립칩 접속부는 96 mΩ의 평균 접속저항을 나타내었다. Soft PDMS/hard PDMS/PTFE 구조의 신축 패키지를 30% 변형률로 인장시 PTFE의 변형률이 1%로 억제되었으며, PTFE 기판에 형성한 회로저항의 중가는 1%로 무시할 정도였다. 0~30% 범위의 신축변형 싸이클을 2,500회 반복시 회로저항이 1.7% 증가하였다.

• 대한금속재료학회지
• /
• 제49권5호
• /
• pp.411-418
• /
• 2011

The current study investigates the electroplating characteristics of Sn-Cu eutectic micro-bumps electroplated on a Si chip for flip chip application. Under bump metallization (UBM) layers consisting of Cr, Cu, Ni and Au sequentially from bottom to top with the aim of achieving Sn-Cu bumps $10\times10\times6$ ${\mu}m$ in size, with 20${\mu}m$ pitch. In order to determine optimal plating parameters, the polarization curve, current density and plating time were analyzed. Experimental results showed the equilibrium potential from the Sn-Cu polarization curve is -0.465 V, which is attained when Sn-Cu electro-deposition occurred. The thickness of the electroplated bumps increased with rising current density and plating time up to 20 mA/$cm^2$ and 30 min respectively. The near eutectic composition of the Sn-0.72wt%Cu bump was obtained by plating at 10 mA/$cm^2$ for 20 min, and the bump size at these conditions was $10\times10\times6$ ${\mu}m$. The shear strength of the eutectic Sn-Cu bump was 9.0 gf when the shearing tip height was 50% of the bump height.

• ETRI Journal
• /
• 제35권6호
• /
• pp.1152-1155
• /
• 2013

A cost-effective and simple solder on pad (SoP) process is proposed for a fine-pitch microbump interconnection. A novel solder bump maker (SBM) material is applied to form a 60-${\mu}m$ pitch SoP. SBM, which is composed of ternary Sn3.0Ag0.5Cu (SAC305) solder powder and a polymer resin, is a paste material used to perform a fine-pitch SoP through a screen printing method. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder, the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. Test vehicles with a daisy chain pattern are fabricated to develop the fine-pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si chip has 6,724 bumps with a 45-${\mu}m$ diameter and 60-${\mu}m$ pitch. The chip is flip chip bonded with a Si substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of the underfill. The optimized bonding process is validated through an electrical characterization of the daisy chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and microbump interconnection using a screen printing process.