• Journal of the Microelectronics and Packaging Society
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• v.12 no.4 s.37
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• pp.315-321
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• 2005

Chip-on-glass technology to attach IC chip directly on the glass substrate of flat panel display was studied by using induction heating body in AC magnetic field. With applying magnetic field of 230 Oe at 14 kHz, the temperature of an induction heating body made with Cu electrodeposited film of 5 mm${\times}$5 mm size and $600{\mu}m$ thickness reached to $250^{\circ}C$ within 60 seconds. However, the temperature of the glass substrate was maintained below $100^{\circ}C$ at a distance larger than 2 mm from the Cu induction heating body. COG bonding was successfully accomplished with reflow of Sn-3.5Ag solder bumps by applying magnetic field of 230 Oe at 14 kHz for 120 seconds to a Cu induction heating body of 5mm${\times}$5mm size and $600{\mu}m$ thickness.

• Proceedings of the KWS Conference
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• 2010.05a
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• pp.78-78
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• 2010

모바일 정보통신기기를 중심으로 패키지의 초소형화, 고집적화를 위해 플립칩 공법의 적용이 증가되고 있고 있으며 접속피치의 미세화에 따라 솔더 및 언더필을 사용하는 C4 공법보다 ACA(Anisotropic Conductive Adhesive), NCA (Non-conductive Adhesive) 등의 접착제를 이용하는 칩본딩 공법에 대한 요구가 증가하고 있다. 특히, NCA 공법의 경우 산업 현장의 대량생산에 대응하기 위해서는 접착제의 속경화 특성이 요구되어 진다. 일반적으로 접착제의 경화거동은 DSC(Differential Scanning Calorimeter)를 사용해 확인하지만, 수초 이내에 경화되는 접착제의 경우는 적용되기 어렵다. 본 연구에서는 이러한 전자패키지용 접착제의 속경화 거동을 효과적으로 평가할 수 있는 방법을 조사 하였다. 실험에서 사용된 접착제는 에폭시계 레진 기반에 이미다졸계 경화제를 사용한 기본적인 포뮬레이션을 사용하였고, 경화시간은 160^{\circ}C에서 1분 이내에 경화되는 특성을 가지고 있다. 경화 거동을 확인하기 위해서 isothermal DSC와 DEA(Dielectric Analysis)의 두가지 방법을 사용해 비교하였다. 두 실험 방법 모두 $160^{\circ}C$를 유지하며 경화 거동을 확인하였고, DoC(Degree of Cure)의 측정오차를 비교 분석하였다. DEA는 이온 모빌리티 변화에 따른 유전손실율을 측정하는 방법으로 80~90% 이후의 경화도는 측정되지 않았지만, 수초 이내에 경화되는 속경화 특성을 평가하기에 적합한 것으로 확인되었다.

• Proceedings of the KIEE Conference
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• 2005.11a
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• pp.30-32
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• 2005

This paper reports on an LTCC-based packaging method using Au/Sn eutectic bonding process for RF MEMS applications. The proposed packaging structure was realized by a micromachining technology. An LTCC substrate consists of metal filled vertical via feedthroughs for electrical interconnection and Au/Sn sealing rim for eutectic bonding. The LTCC capping substrate and the glass bottom substrate were aligned and bonded together by a flip-chip bonding technology. From now on, shear strength and He leak rate will be measured then the fabricated package will be compared with the LTCC package using BCB adhesive bonding method which has been researched in our previous work.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.111-119
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• 2005

Stack specimen with three dimensional interconnection structure through Cu via of $75{\mu}m$ diameter, $90{\mu}m$ height and $150{\mu}m$ pitch was successfully fabricated using subsequent processes of via hole formation with Deep RIE (reactive ion etching), Cu via filling with pulse-reverse electroplating, Si thinning with CMP, photolithography, metal film sputtering, Cu/Sn bump formation, and flip chip bonding. Contact resistance of Cu/Sn bump and Cu via resistance could be determined ken the slope of the daisy chain resistance vs the number of bump joints of the flip chip specimen containing Cu via. When flip- chip bonded at $270^{\circ}C$ for 2 minutes, the contact resistance of the Cu/Sn bump joints of $100{\times}100{\mu}m$ size was 6.7m$\Omega$ and the Cu via resistance of $75{\mu}m$ diameter, $90{\mu}m$ height was 2.3m$\Omega$.

• Korean Journal of Metals and Materials
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• v.47 no.7
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• pp.447-453
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• 2009

Isotropic conductive adhesives (ICAs) have been used or considered as an interconnect material for radio frequency identification (RFID) inlays or other flip chip assemblies due to the advantages of having a low temperature and high-speed bonding. In this work, the curing properties of commercial ICAs for the RFID tag application and the signal transmission in conductive lines that contained the ICA joints were evaluated as a function of the degree of cure at 900 MHz frequency range. The ICAs showed adequate signal transmission only after the curing process passed over the critical time. It was also found that the insertion loss of signal was more dependent on the contact states of Ag fillers in the bondline in preference to the electrical resistance of the ICA itself.

• ETRI Journal
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• v.37 no.2
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• pp.387-394
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• 2015

A novel interconnection technology based on a 52InSn solder was developed for flexible display applications. The display industry is currently trying to develop a flexible display, and one of the crucial technologies for the implementation of a flexible display is to reduce the bonding process temperature to less than $150^{\circ}C$. InSn solder interconnection technology is proposed herein to reduce the electrical contact resistance and concurrently achieve a process temperature of less than $150^{\circ}C$. A solder bump maker (SBM) and fluxing underfill were developed for these purposes. SBM is a novel bumping material, and it is a mixture of a resin system and InSn solder powder. A maskless screen printing process was also developed using an SBM to reduce the cost of the bumping process. Fluxing underfill plays the role of a flux and an underfill concurrently to simplify the bonding process compared to a conventional flip-chip bonding using a capillary underfill material. Using an SBM and fluxing underfill, a $20{\mu}m$ pitch InSn solder SoP array on a glass substrate was successfully formed using a maskless screen printing process, and two glass substrates were bonded at $130^{\circ}C$.

• Journal of the Korean institute of surface engineering
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• v.50 no.3
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• pp.170-176
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• 2017

EPIG (Electroless Pd/immersion Au) process was studied to replace ENIG (electroless Ni/immersion Au) and ENEPIG (electroless Ni/electroless Pd/immersion Au) processes for bump surface treatment used in high reliable flip chip packages. The palladium and gold layers formed by EPIG process were uniform with thickness of 125 nm and 34.5 nm, respectively. EPAG (Electroless Pd/autocatalytic Au) also produced even layers of palladium and gold with the thickness of 115 nm and 100 nm. TEM results exhibited that the gold layer in EPIG surface had crystalline structure while the palladium layer was amorphous one. After annealing at 250 nm, XPS analysis indicated that the palladium layer with thickness more than 22~33 nm could act as a diffusion barrier of copper interconnects. As a result of comparing the chip shear strength obtained from ENIG and EPIG surfaces, it was confirmed that the bonding strength was similar each other as 12.337 kg and 12.330 kg, respectively.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.4
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• pp.47-53
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• 2019

Stiffness-gradient stretchable electronic packages of the soft PDMS/hard PDMS/PTFE structure were processed using the polydimethylsiloxane (PDMS) as the base substrate and the more stiff polytetrafluoroethylene (PTFE) as the island substrate, and their stretchable deformation-resistance characteristics were characterized. The flip-chip joints, formed by bonding the chip bumps of 50 ㎛-diameter onto the PDMS/PTFE substrate pads, exhibited an average contact resistance of 96 mΩ. When the stretchable package of the soft PDMS/hard PDMS/PTFE structure was deformed to 30% elongation, the strain on the PTFE was restrained to 1%, resulting in a negligible resistance increase of 1% in the daisy-chain circuit formed on the PTFE island substrate. The circuit resistance increased for 1.7% after 2,500 cycles of 0~30% stretchable deformation.

• Korean Journal of Metals and Materials
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• v.49 no.5
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• pp.411-418
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• 2011

The current study investigates the electroplating characteristics of Sn-Cu eutectic micro-bumps electroplated on a Si chip for flip chip application. Under bump metallization (UBM) layers consisting of Cr, Cu, Ni and Au sequentially from bottom to top with the aim of achieving Sn-Cu bumps $10\times10\times6$ ${\mu}m$ in size, with 20${\mu}m$ pitch. In order to determine optimal plating parameters, the polarization curve, current density and plating time were analyzed. Experimental results showed the equilibrium potential from the Sn-Cu polarization curve is -0.465 V, which is attained when Sn-Cu electro-deposition occurred. The thickness of the electroplated bumps increased with rising current density and plating time up to 20 mA/$cm^2$ and 30 min respectively. The near eutectic composition of the Sn-0.72wt%Cu bump was obtained by plating at 10 mA/$cm^2$ for 20 min, and the bump size at these conditions was $10\times10\times6$ ${\mu}m$. The shear strength of the eutectic Sn-Cu bump was 9.0 gf when the shearing tip height was 50% of the bump height.

• ETRI Journal
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• v.35 no.6
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• pp.1152-1155
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• 2013

A cost-effective and simple solder on pad (SoP) process is proposed for a fine-pitch microbump interconnection. A novel solder bump maker (SBM) material is applied to form a 60-${\mu}m$ pitch SoP. SBM, which is composed of ternary Sn3.0Ag0.5Cu (SAC305) solder powder and a polymer resin, is a paste material used to perform a fine-pitch SoP through a screen printing method. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder, the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. Test vehicles with a daisy chain pattern are fabricated to develop the fine-pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si chip has 6,724 bumps with a 45-${\mu}m$ diameter and 60-${\mu}m$ pitch. The chip is flip chip bonded with a Si substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of the underfill. The optimized bonding process is validated through an electrical characterization of the daisy chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and microbump interconnection using a screen printing process.